x86: coreboot: Look for DBG2 UART in SPL too

If coreboot does not set up sysinfo for the UART, SPL currently hangs.
Use the DBG2 technique there as well. This allows coreboot64 to boot from
coreboot even if the console info is missing from sysinfo

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
index 5623197f6be24d630bedcd2d7c44d58f5cd30669..e8165961c1992b3ca29707e468b06c0a018d072a 100644 (file)
--- a/configs/coreboot64_defconfig
+++ b/configs/coreboot64_defconfig
@@ -54,4 +54,5 @@ CONFIG_SYS_64BIT_LBA=y
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
 CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_SPL_ACPI=y
 # CONFIG_GZIP is not set

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 7ca42df6a7e27782fd8424b05959d19ec5c7cc83..27b4b9d9650785db0000878307bfa534b842ec08 100644 (file)
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -672,7 +672,7 @@ config COREBOOT_SERIAL
 config COREBOOT_SERIAL_FROM_DBG2
        bool "Obtain UART from ACPI tables"
        depends on COREBOOT_SERIAL
-       default y if !SPL
+       default y
        help
          Select this to try to find a DBG2 record in the ACPI tables, in the
          event that coreboot does not provide information about the UART in the