powerpc/85xx: Fix PCI memory map setup on P1_P2_RDB

Update the PCIe address map to match standard FSL memory map.
Additionally, fix the TLBs so the cover the PCIe address space properly
so cards plugged in like an e1000 work correctly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index b85c268db538f0a9ac77c557f41a2bdd2ac97de5..a46b1b5670a83f0697ddf1f788b173074b08fd94 100644 (file)
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -60,12 +60,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_PCI)
        /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 3, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 4, BOOKE_PAGESZ_256K, 1),
 

diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 982cdd501596dc92456c593a4e14b06cc71a413c..95b85e3f6578f74b106e43b315897815b68ccd10 100644 (file)
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -177,8 +177,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Memory map
  *
  * 0x0000_0000 0x3fff_ffff     DDR                     1G cacheablen
- * 0xa000_0000 0xbfff_ffff     PCI Express Mem         1G non-cacheable
- * 0xffc2_0000 0xffc5_ffff     PCI IO range            256K non-cacheable
+ * 0x8000_0000  0xbfff_ffff    PCI Express Mem         1G non-cacheable
+ * 0xffc0_0000  0xffc3_ffff    PCI IO range            256k non-cacheable
  *
  * Localbus cacheable (TBD)
  * 0xXXXX_XXXX 0xXXXX_XXXX     SRAM                    YZ M Cacheable
@@ -368,27 +368,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #if defined(CONFIG_PCI)
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_NAME          "Slot 1"
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc20000
-#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc20000
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_NAME          "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT      0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc30000
-#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc30000
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc00000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play */