phy: ti-pipe3: Use TRM recommended settings for SATA DPLL

The AM572x Technical Reference Manual, SPRUHZ6H,
Revised November 2016 [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.

Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.

[1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf

Signed-off-by: Roger Quadros <rogerq@ti.com>

diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c
index e7e78e3c56d71a6bc58dde0c80260b91d649fd7f..f3b071399c7fa16ffd39eacfbee5061ef469d5a1 100644 (file)
--- a/drivers/phy/ti-pipe3-phy.c
+++ b/drivers/phy/ti-pipe3-phy.c
@@ -346,13 +346,13 @@ static int pipe3_phy_probe(struct udevice *dev)
 }
 
 static struct pipe3_dpll_map dpll_map_sata[] = {
-       {12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
-       {16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
-       {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
-       {20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
-       {26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
-       {38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
-       { },                                    /* Terminator */
+       {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
+       {16800000, {625, 6, 4, 7, 0} },         /* 16.8 MHz */
+       {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
+       {20000000, {750, 9, 4, 6, 0} },         /* 20 MHz */
+       {26000000, {750, 12, 4, 6, 0} },        /* 26 MHz */
+       {38400000, {625, 15, 4, 6, 0} },        /* 38.4 MHz */
+       { },                                    /* Terminator */
 };
 
 static struct pipe3_dpll_map dpll_map_usb[] = {