x86: dts: Move PCI peripherals into a pci node

These peripherals should not be at the top level, since they exist inside
the PCI bus. We don't have a full device tree node for pci yet, but we
should at least put it at the right level.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 932991604f7c9503af72210faefddebbabf941b9..4520db5bca98947f293b4de2e0af40fbbadf7338 100644 (file)
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -163,21 +163,23 @@
                };
        };
 
-       lpc {
-               compatible = "intel,lpc";
-               #address-cells = <1>;
-               #size-cells = <1>;
-               gen-dec = <0x800 0xfc 0x900 0xfc>;
-               cros-ec@200 {
-                       compatible = "google,cros-ec";
-                       reg = <0x204 1 0x200 1 0x880 0x80>;
-
-                       /* This describes the flash memory within the EC */
+       pci {
+               lpc {
+                       compatible = "intel,lpc";
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       flash@8000000 {
-                               reg = <0x08000000 0x20000>;
-                               erase-value = <0xff>;
+                       gen-dec = <0x800 0xfc 0x900 0xfc>;
+                       cros-ec@200 {
+                               compatible = "google,cros-ec";
+                               reg = <0x204 1 0x200 1 0x880 0x80>;
+
+                               /* Describes the flash memory within the EC */
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               flash@8000000 {
+                                       reg = <0x08000000 0x20000>;
+                                       erase-value = <0xff>;
+                               };
                        };
                };
        };