ls1021aqds: set the default I2C channel before DDR init

When resuming from deep sleep, the I2C channel may not be
in the default channel. So, switch to the default channel
before accessing DDR SPD.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d7813d90c0c3e615c10e57ed216d0d720536760a..bf22fced9c4662a15de311e96d6177996df59b27 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -102,8 +102,27 @@ unsigned long get_board_ddr_clk(void)
        return 66666666;
 }
 
+int select_i2c_ch_pca9547(u8 ch)
+{
+       int ret;
+
+       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+       if (ret) {
+               puts("PCA: failed to select proper channel\n");
+               return ret;
+       }
+
+       return 0;
+}
+
 int dram_init(void)
 {
+       /*
+        * When resuming from deep sleep, the I2C channel may not be
+        * in the default channel. So, switch to the default channel
+        * before accessing DDR SPD.
+        */
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
        gd->ram_size = initdram(0);
 
        return 0;
@@ -122,19 +141,6 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-int select_i2c_ch_pca9547(u8 ch)
-{
-       int ret;
-
-       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-       if (ret) {
-               puts("PCA: failed to select proper channel\n");
-               return ret;
-       }
-
-       return 0;
-}
-
 int board_early_init_f(void)
 {
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;