watchdog: Add reset support for OcteonTX / TX2

Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2
platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0ebf116b129053647909ee96e58476498dc8d9b7..210d9f8093dd370dc457b0aeff3ce947b40a3ba8 100644 (file)
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -139,6 +139,16 @@ config WDT_MTK
          The watchdog timer is stopped when initialized.
          It performs full SoC reset.
 
+config WDT_OCTEONTX
+       bool "OcteonTX core watchdog support"
+       depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
+       default y
+       imply WATCHDOG
+       help
+         This enables OcteonTX watchdog driver, which can be
+         found on OcteonTX/TX2 chipsets and inline with driver model.
+         Only supports watchdog reset.
+
 config WDT_OMAP3
        bool "TI OMAP watchdog timer support"
        depends on WDT && ARCH_OMAP2PLUS

diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 111e25819527cb211cada9202a4eea3156ad638d..01b8231f2bf6262f756cd323e0b69066e73b23bd 100644 (file)
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
 obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
 obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
 obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
 obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
 obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
 obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o

diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c
new file mode 100644 (file)
index 0000000..1e0670e
--- /dev/null
+++ b/drivers/watchdog/octeontx_wdt.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <wdt.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CORE0_POKE_OFFSET      0x50000
+#define CORE0_POKE_OFFSET_MASK 0xfffffULL
+
+struct octeontx_wdt {
+       void __iomem *reg;
+};
+
+static int octeontx_wdt_reset(struct udevice *dev)
+{
+       struct octeontx_wdt *priv = dev_get_priv(dev);
+
+       writeq(~0ULL, priv->reg);
+
+       return 0;
+}
+
+static int octeontx_wdt_probe(struct udevice *dev)
+{
+       struct octeontx_wdt *priv = dev_get_priv(dev);
+
+       priv->reg = dev_remap_addr(dev);
+       if (!priv->reg)
+               return -EINVAL;
+
+       /*
+        * Save core poke register address in reg (its not 0xa0000 as
+        * extracted from the DT but 0x50000 instead)
+        */
+       priv->reg = (void __iomem *)(((u64)priv->reg &
+                                     ~CORE0_POKE_OFFSET_MASK) |
+                                    CORE0_POKE_OFFSET);
+
+       return 0;
+}
+
+static const struct wdt_ops octeontx_wdt_ops = {
+       .reset = octeontx_wdt_reset,
+};
+
+static const struct udevice_id octeontx_wdt_ids[] = {
+       { .compatible = "arm,sbsa-gwdt" },
+       {}
+};
+
+U_BOOT_DRIVER(wdt_octeontx) = {
+       .name = "wdt_octeontx",
+       .id = UCLASS_WDT,
+       .of_match = octeontx_wdt_ids,
+       .ops = &octeontx_wdt_ops,
+       .priv_auto_alloc_size = sizeof(struct octeontx_wdt),
+       .probe = octeontx_wdt_probe,
+};