clk: ast2600: Add RSACLK control for ACRY

Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine
of ASPEED AST2600 SoCs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
index d7b500f65666288262401690413b7bed41c81d4b..7c5aab98b636104a1cbf0abbf3892b23d0ff73b9 100644 (file)
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
@@ -8,6 +8,7 @@
 #define SCU_UNLOCK_KEY                 0x1688a8a8
 
 #define SCU_CLKGATE1_EMMC                      BIT(27)
+#define SCU_CLKGATE1_ACRY                      BIT(24)
 #define SCU_CLKGATE1_MAC2                      BIT(21)
 #define SCU_CLKGATE1_MAC1                      BIT(20)
 #define SCU_CLKGATE1_USB_HUB                   BIT(14)

diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 9871a6bdbfddc58e236d9a8687862126b76be169..42ca39421cff7c04af530cafae449cfb1888f649 100644 (file)
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -1018,6 +1018,7 @@ static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
        uint32_t reset_bit;
        uint32_t clkgate_bit;
 
+       /* share the same reset control bit with ACRY */
        reset_bit = BIT(ASPEED_RESET_HACE);
        clkgate_bit = SCU_CLKGATE1_HACE;
 
@@ -1032,6 +1033,26 @@ static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
        return 0;
 }
 
+static ulong ast2600_enable_rsaclk(struct ast2600_scu *scu)
+{
+       uint32_t reset_bit;
+       uint32_t clkgate_bit;
+
+       /* same reset control bit with HACE */
+       reset_bit = BIT(ASPEED_RESET_HACE);
+       clkgate_bit = SCU_CLKGATE1_ACRY;
+
+       /*
+        * we don't do reset assertion here as HACE
+        * shares the same reset control with ACRY
+        */
+       writel(clkgate_bit, &scu->clkgate_clr1);
+       mdelay(20);
+       writel(reset_bit, &scu->modrst_clr1);
+
+       return 0;
+}
+
 static int ast2600_clk_enable(struct clk *clk)
 {
        struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
@@ -1073,6 +1094,9 @@ static int ast2600_clk_enable(struct clk *clk)
        case ASPEED_CLK_GATE_YCLK:
                ast2600_enable_haceclk(priv->scu);
                break;
+       case ASPEED_CLK_GATE_RSACLK:
+               ast2600_enable_rsaclk(priv->scu);
+               break;
        default:
                pr_err("can't enable clk\n");
                return -ENOENT;