IMAGE_CFG_NAND_BADBLK_LOCATION,
IMAGE_CFG_NAND_ECC_MODE,
IMAGE_CFG_NAND_PAGESZ,
+ IMAGE_CFG_CPU,
IMAGE_CFG_BINARY,
IMAGE_CFG_DATA,
IMAGE_CFG_DATA_DELAY,
[IMAGE_CFG_NAND_BADBLK_LOCATION] = "NAND_BADBLK_LOCATION",
[IMAGE_CFG_NAND_ECC_MODE] = "NAND_ECC_MODE",
[IMAGE_CFG_NAND_PAGESZ] = "NAND_PAGE_SIZE",
+ [IMAGE_CFG_CPU] = "CPU",
[IMAGE_CFG_BINARY] = "BINARY",
[IMAGE_CFG_DATA] = "DATA",
[IMAGE_CFG_DATA_DELAY] = "DATA_DELAY",
enum image_cfg_type type;
union {
unsigned int version;
+ unsigned int cpu_sheeva;
unsigned int bootfrom;
struct {
const char *file;
return e->bootfrom;
}
+static int image_is_cpu_sheeva(void)
+{
+ struct image_cfg_element *e;
+
+ e = image_find_option(IMAGE_CFG_CPU);
+ if (!e)
+ return 0;
+
+ return e->cpu_sheeva;
+}
+
/*
* Compute a 8-bit checksum of a memory area. This algorithm follows
* the requirements of the Marvell SoC BootROM specifications.
case IMAGE_CFG_VERSION:
el->version = atoi(value1);
break;
+ case IMAGE_CFG_CPU:
+ if (strcmp(value1, "FEROCEON") == 0)
+ el->cpu_sheeva = 0;
+ else if (strcmp(value1, "SHEEVA") == 0)
+ el->cpu_sheeva = 1;
+ else if (strcmp(value1, "A9") == 0)
+ el->cpu_sheeva = 0;
+ else {
+ fprintf(stderr, "Invalid CPU %s\n", value1);
+ return -1;
+ }
+ break;
case IMAGE_CFG_BOOT_FROM:
ret = image_boot_mode_id(value1);