powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured support

Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d491e2ad5a521d80055bd3e5aaf123a39492efeb..5d5b4c2963609d6b307da8e7f3f14e64c299a23d 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -39,10 +39,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_MPC8536
-extern void fsl_serdes_init(void);
-#endif
-
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -185,9 +181,6 @@ void cpu_init_f (void)
        /* Config QE ioports */
        config_qe_ioports();
 #endif
-#if defined(CONFIG_MPC8536)
-       fsl_serdes_init();
-#endif
 #if defined(CONFIG_FSL_DMA)
        dma_init();
 #endif
@@ -332,6 +325,11 @@ int cpu_init_r(void)
        qe_reset();
 #endif
 
+#if defined(CONFIG_SYS_HAS_SERDES)
+       /* needs to be in ram since code uses global static vars */
+       fsl_serdes_init();
+#endif
+
 #if defined(CONFIG_MP)
        setup_mp();
 #endif

diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index 7e72f5fb7c78958af989f019f45870c469e4594d..6dadeb8cabc7d9fc3a3d9c133d63a47b959b0a07 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -66,10 +66,11 @@
 #define FSL_SRDSCR3_LANEE_SGMII        0x00000000
 #define FSL_SRDSCR3_LANEE_SATA 0x00150005
 
-
 #define SRDS1_MAX_LANES                8
 #define SRDS2_MAX_LANES                2
 
+static u32 serdes1_prtcl_map, serdes2_prtcl_map;
+
 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
        [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
        [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
@@ -86,39 +87,12 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
 
 int is_serdes_configured(enum srds_prtcl device)
 {
-       int i;
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       u32 pordevsr = in_be32(&gur->pordevsr);
-       u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-                               MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+       int ret = (1 << device) & serdes1_prtcl_map;
 
-       u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >>
-                               GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
-
-       debug("%s: dev = %d\n", __FUNCTION__, device);
-       debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
-       debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg);
-
-       if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
-               printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
-               return 0;
-       }
-
-       if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
-               printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg);
-               return 0;
-       }
-
-       for (i = 0; i < SRDS1_MAX_LANES; i++) {
-               if (serdes1_cfg_tbl[srds1_cfg][i] == device)
-                       return 1;
-       }
-       for (i = 0; i < SRDS2_MAX_LANES; i++) {
-               if (serdes2_cfg_tbl[srds2_cfg][i] == device)
-                       return 1;
-       }
+       if (ret)
+               return ret;
 
-       return 0;
+       return (1 << device) & serdes2_prtcl_map;
 }
 
 void fsl_serdes_init(void)
@@ -126,13 +100,20 @@ void fsl_serdes_init(void)
        void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
        u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
-       u32 srds2_io_sel;
+       u32 srds1_io_sel, srds2_io_sel;
        u32 tmp;
+       int lane;
+
+       srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+                               MPC85xx_PORDEVSR_IO_SEL_SHIFT;
 
        /* parse the SRDS2_IO_SEL of PORDEVSR */
        srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
                       >> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
 
+       debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel);
+       debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel);
+
        switch (srds2_io_sel) {
        case 1: /* Lane A - SATA1, Lane E - SATA2 */
                /* CR 0 */
@@ -246,4 +227,23 @@ void fsl_serdes_init(void)
        default:
                break;
        }
+
+       if (srds1_io_sel > ARRAY_SIZE(serdes1_cfg_tbl)) {
+               printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
+               return;
+       }
+       for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+               enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane];
+               serdes1_prtcl_map |= (1 << lane_prtcl);
+       }
+
+       if (srds2_io_sel > ARRAY_SIZE(serdes2_cfg_tbl)) {
+               printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
+               return;
+       }
+
+       for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
+               enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
+               serdes2_prtcl_map |= (1 << lane_prtcl);
+       }
 }

diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index d4839f4673f5c5b3c7c6ff6c6b0b62859db16dc2..c7877b91a18920c1cd2bdeea4137a6868cd291e9 100644 (file)
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -44,5 +44,6 @@ enum srds_prtcl {
 };
 
 int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
 
 #endif /* __FSL_SERDES_H */

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 24a75c601180e5d1c82624bd4dfda9cc0669f488..890a6c9bc452c8f49308afd85a502de10ec74043 100644 (file)
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -65,6 +65,7 @@
 #define CONFIG_FSL_PCI_INIT    1       /* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET  1       /* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
+#define CONFIG_SYS_HAS_SERDES          /* has SERDES */
 
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 #define CONFIG_E1000           1       /* Defind e1000 pci Ethernet card*/