ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms

- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index afb94cc07004533aedc92f9ba33e0cbd2cd16d6b..01ab523c51207522e87e256cfec732febb3eb2ab 100644 (file)
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -112,7 +112,7 @@ cpu_init_f (void)
        unsigned long val;
 #endif
 
-#if defined(CONFIG_405EP) || defined (CONFIG_405EX)
+#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
        /*
         * GPIO0 setup (select GPIO or alternate function)
         */
@@ -144,9 +144,9 @@ cpu_init_f (void)
 #endif /* CONFIG_405EP */
 #endif /* CONFIG_405EP */
 
-#if defined(CFG_440_GPIO_TABLE)
+#if defined(CFG_4xx_GPIO_TABLE)
        gpio_set_chip_configuration();
-#endif /* CFG_440_GPIO_TABLE */
+#endif /* CFG_4xx_GPIO_TABLE */
 
        /*
         * External Bus Controller (EBC) Setup

diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c
index 50f2fdf1139cfbbb049fd7377a66de187d175bf8..dcf1fba8384d7d5603b33daa9c59c775b50bd96c 100644 (file)
--- a/cpu/ppc4xx/gpio.c
+++ b/cpu/ppc4xx/gpio.c
@@ -26,8 +26,8 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
-#if defined(CFG_440_GPIO_TABLE)
-gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
+#if defined(CFG_4xx_GPIO_TABLE)
+gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
 #endif
 
 #if defined(GPIO0_OSRL)
@@ -55,10 +55,10 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
        mask2 = 0xc0000000 >> (pin2 << 1);
 
        /* first set TCR to 0 */
-       out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask);
+       out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask);
 
        if (in_out == GPIO_OUT) {
-               val = in32(GPIO0_OSRL + offs + offs2) & ~mask2;
+               val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
                switch (gpio_alt) {
                case GPIO_ALT1:
                        val |= GPIO_ALT1_SEL >> pin2;
@@ -70,20 +70,23 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
                        val |= GPIO_ALT3_SEL >> pin2;
                        break;
                }
-               out32(GPIO0_OSRL + offs + offs2, val);
+               out_be32((void *)GPIO0_OSRL + offs + offs2, val);
 
                /* setup requested output value */
                if (out_val == GPIO_OUT_0)
-                       out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask);
+                       out_be32((void *)GPIO0_OR + offs,
+                                in_be32((void *)GPIO0_OR + offs) & ~mask);
                else if (out_val == GPIO_OUT_1)
-                       out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask);
+                       out_be32((void *)GPIO0_OR + offs,
+                                in_be32((void *)GPIO0_OR + offs) | mask);
 
                /* now configure TCR to drive output if selected */
-               out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask);
+               out_be32((void *)GPIO0_TCR + offs,
+                        in_be32((void *)GPIO0_TCR + offs) | mask);
        } else {
-               val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2;
+               val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
                val |= GPIO_IN_SEL >> pin2;
-               out32(GPIO0_ISR1L + offs + offs2, val);
+               out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
        }
 }
 #endif /* GPIO_OSRL */
@@ -98,9 +101,11 @@ void gpio_write_bit(int pin, int val)
        }
 
        if (val)
-               out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin));
+               out_be32((void *)GPIO0_OR + offs,
+                        in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin));
        else
-               out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
+               out_be32((void *)GPIO0_OR + offs,
+                        in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
 }
 
 int gpio_read_out_bit(int pin)
@@ -112,10 +117,10 @@ int gpio_read_out_bit(int pin)
                pin -= GPIO_MAX;
        }
 
-       return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
+       return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
 }
 
-#if defined(CFG_440_GPIO_TABLE)
+#if defined(CFG_4xx_GPIO_TABLE)
 void gpio_set_chip_configuration(void)
 {
        unsigned char i=0, j=0, offs=0, gpio_core;
@@ -141,24 +146,24 @@ void gpio_set_chip_configuration(void)
                                        break;
 
                                case GPIO_ALT1:
-                                       reg = in32(GPIO_IS1(core_add+offs))
+                                       reg = in_be32((void *)GPIO_IS1(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
                                        reg = reg | (GPIO_IN_SEL >> (j*2));
-                                       out32(GPIO_IS1(core_add+offs), reg);
+                                       out_be32((void *)GPIO_IS1(core_add+offs), reg);
                                        break;
 
                                case GPIO_ALT2:
-                                       reg = in32(GPIO_IS2(core_add+offs))
+                                       reg = in_be32((void *)GPIO_IS2(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
                                        reg = reg | (GPIO_IN_SEL >> (j*2));
-                                       out32(GPIO_IS2(core_add+offs), reg);
+                                       out_be32((void *)GPIO_IS2(core_add+offs), reg);
                                        break;
 
                                case GPIO_ALT3:
-                                       reg = in32(GPIO_IS3(core_add+offs))
+                                       reg = in_be32((void *)GPIO_IS3(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
                                        reg = reg | (GPIO_IN_SEL >> (j*2));
-                                       out32(GPIO_IS3(core_add+offs), reg);
+                                       out_be32((void *)GPIO_IS3(core_add+offs), reg);
                                        break;
                                }
                        }
@@ -168,87 +173,66 @@ void gpio_set_chip_configuration(void)
 
                                switch (gpio_tab[gpio_core][i].alt_nb) {
                                case GPIO_SEL:
-                                       if (gpio_core == GPIO0) {
-                                               /*
-                                                * Setup output value
-                                                * 1 -> high level
-                                                * 0 -> low level
-                                                * else -> don't touch
-                                                */
-                                               reg = in32(GPIO0_OR);
-                                               if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
-                                                       reg |= (0x80000000 >> (i));
-                                               else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
-                                                       reg &= ~(0x80000000 >> (i));
-                                               out32(GPIO0_OR, reg);
-
-                                               reg = in32(GPIO0_TCR) | (0x80000000 >> (i));
-                                               out32(GPIO0_TCR, reg);
-                                       }
-
-#ifdef GPIO1
-                                       if (gpio_core == GPIO1) {
-                                               /*
-                                                * Setup output value
-                                                * 1 -> high level
-                                                * 0 -> low level
-                                                * else -> don't touch
-                                                */
-                                               reg = in32(GPIO1_OR);
-                                               if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
-                                                       reg |= (0x80000000 >> (i));
-                                               else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
-                                                       reg &= ~(0x80000000 >> (i));
-                                               out32(GPIO1_OR, reg);
-
-                                               reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
-                                               out32(GPIO1_TCR, reg);
-                                       }
-#endif /* GPIO1 */
-
-                                       reg = in32(GPIO_OS(core_add+offs))
+                                       /*
+                                        * Setup output value
+                                        * 1 -> high level
+                                        * 0 -> low level
+                                        * else -> don't touch
+                                        */
+                                       reg = in_be32((void *)GPIO_OR(core_add));
+                                       if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
+                                               reg |= (0x80000000 >> (i));
+                                       else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
+                                               reg &= ~(0x80000000 >> (i));
+                                       out_be32((void *)GPIO_OR(core_add), reg);
+
+                                       reg = in_be32((void *)GPIO_TCR(core_add)) |
+                                               (0x80000000 >> (i));
+                                       out_be32((void *)GPIO_TCR(core_add), reg);
+
+                                       reg = in_be32((void *)GPIO_OS(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
-                                       out32(GPIO_OS(core_add+offs), reg);
-                                       reg = in32(GPIO_TS(core_add+offs))
+                                       out_be32((void *)GPIO_OS(core_add+offs), reg);
+                                       reg = in_be32((void *)GPIO_TS(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
-                                       out32(GPIO_TS(core_add+offs), reg);
+                                       out_be32((void *)GPIO_TS(core_add+offs), reg);
                                        break;
 
                                case GPIO_ALT1:
-                                       reg = in32(GPIO_OS(core_add+offs))
+                                       reg = in_be32((void *)GPIO_OS(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
                                        reg = reg | (GPIO_ALT1_SEL >> (j*2));
-                                       out32(GPIO_OS(core_add+offs), reg);
-                                       reg = in32(GPIO_TS(core_add+offs))
+                                       out_be32((void *)GPIO_OS(core_add+offs), reg);
+                                       reg = in_be32((void *)GPIO_TS(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
                                        reg = reg | (GPIO_ALT1_SEL >> (j*2));
-                                       out32(GPIO_TS(core_add+offs), reg);
+                                       out_be32((void *)GPIO_TS(core_add+offs), reg);
                                        break;
 
                                case GPIO_ALT2:
-                                       reg = in32(GPIO_OS(core_add+offs))
+                                       reg = in_be32((void *)GPIO_OS(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
                                        reg = reg | (GPIO_ALT2_SEL >> (j*2));
-                                       out32(GPIO_OS(core_add+offs), reg);
-                                       reg = in32(GPIO_TS(core_add+offs))
+                                       out_be32((void *)GPIO_OS(core_add+offs), reg);
+                                       reg = in_be32((void *)GPIO_TS(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
                                        reg = reg | (GPIO_ALT2_SEL >> (j*2));
-                                       out32(GPIO_TS(core_add+offs), reg);
+                                       out_be32((void *)GPIO_TS(core_add+offs), reg);
                                        break;
 
                                case GPIO_ALT3:
-                                       reg = in32(GPIO_OS(core_add+offs))
+                                       reg = in_be32((void *)GPIO_OS(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
                                        reg = reg | (GPIO_ALT3_SEL >> (j*2));
-                                       out32(GPIO_OS(core_add+offs), reg);
-                                       reg = in32(GPIO_TS(core_add+offs))
+                                       out_be32((void *)GPIO_OS(core_add+offs), reg);
+                                       reg = in_be32((void *)GPIO_TS(core_add+offs))
                                                & ~(GPIO_MASK >> (j*2));
                                        reg = reg | (GPIO_ALT3_SEL >> (j*2));
-                                       out32(GPIO_TS(core_add+offs), reg);
+                                       out_be32((void *)GPIO_TS(core_add+offs), reg);
                                        break;
                                }
                        }
                }
        }
 }
-#endif /* CFG_440_GPIO_TABLE */
+#endif /* CFG_4xx_GPIO_TABLE */

diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h
index c9b6a36b4f95a3934041d9ba713e1b5033deda26..d0c3eba88468206725bb0e317de86b28f68ded94 100644 (file)
--- a/include/asm-ppc/gpio.h
+++ b/include/asm-ppc/gpio.h
@@ -21,6 +21,9 @@
  * MA 02111-1307 USA
  */
 
+#ifndef __ASM_PPC_GPIO_H
+#define __ASM_PPC_GPIO_H
+
 /* 4xx PPC's have 2 GPIO controllers */
 #if defined(CONFIG_405EZ) ||                                   \
        defined(CONFIG_440EP) || defined(CONFIG_440GR) ||       \
@@ -30,6 +33,36 @@
 #define GPIO_GROUP_MAX 1
 #endif
 
+/* Offsets */
+#define GPIOx_OR       0x00            /* GPIO Output Register */
+#define GPIOx_TCR      0x04            /* GPIO Three-State Control Register */
+#define GPIOx_OSL      0x08            /* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH      0x0C            /* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL      0x10            /* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH      0x14            /* GPIO Three-State Select Register  (Bits 32-63) */
+#define GPIOx_ODR      0x18            /* GPIO Open drain Register */
+#define GPIOx_IR       0x1C            /* GPIO Input Register */
+#define GPIOx_RR1      0x20            /* GPIO Receive Register 1 */
+#define GPIOx_RR2      0x24            /* GPIO Receive Register 2 */
+#define GPIOx_RR3      0x28            /* GPIO Receive Register 3 */
+#define GPIOx_IS1L     0x30            /* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H     0x34            /* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L     0x38            /* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H     0x3C            /* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L     0x40            /* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H     0x44            /* GPIO Input Select Register 3 (Bits 32-63) */
+
+#define GPIO_OR(x)     (x+GPIOx_OR)    /* GPIO Output Register */
+#define GPIO_TCR(x)    (x+GPIOx_TCR)   /* GPIO Three-State Control Register */
+#define GPIO_OS(x)     (x+GPIOx_OSL)   /* GPIO Output Select Register High or Low */
+#define GPIO_TS(x)     (x+GPIOx_TSL)   /* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x)    (x+GPIOx_IS1L)  /* GPIO Input register1 High or Low */
+#define GPIO_IS2(x)    (x+GPIOx_IS2L)  /* GPIO Input register2 High or Low */
+#define GPIO_IS3(x)    (x+GPIOx_IS3L)  /* GPIO Input register3 High or Low */
+
+#define GPIO0          0
+#define GPIO1          1
+
 #define GPIO_MAX       32
 #define GPIO_ALT1_SEL  0x40000000
 #define GPIO_ALT2_SEL  0x80000000
@@ -56,3 +89,5 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
 void gpio_write_bit(int pin, int val);
 int gpio_read_out_bit(int pin);
 void gpio_set_chip_configuration(void);
+
+#endif /* __ASM_PPC_GPIO_H */

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 3180617b1e0614d5af790317d7f435506d85972a..9cb483d3ca7665c261ef18af2ff3e4651135f19b 100644 (file)
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -414,7 +414,7 @@
 /*-----------------------------------------------------------------------
  * PPC440 GPIO Configuration
  */
-#define CFG_440_GPIO_TABLE { /*          Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
+#define CFG_4xx_GPIO_TABLE { /*          Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 {                                                                                      \
 /* GPIO Core 0 */                                                                      \
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0        EBC_ADDR(7)     DMA_REQ(2)      */      \

diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index d467338e920add6025f65cc75b5d47f88908e75b..d66f4bd449b5498b388c181cc1ce6aa20901003c 100644 (file)
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -365,7 +365,7 @@
 /*-----------------------------------------------------------------------
  * PPC440 GPIO Configuration
  */
-#define CFG_440_GPIO_TABLE { /*          Out                  GPIO     Alternate1      Alternate2   Alternate3 */ \
+#define CFG_4xx_GPIO_TABLE { /*          Out                  GPIO     Alternate1      Alternate2   Alternate3 */ \
 {                                                                                      \
 /* GPIO Core 0 */                                                                      \
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO0   EBC_ADDR(7)     DMA_REQ(2)      */ \

diff --git a/include/ppc405.h b/include/ppc405.h
index 2c5591726c3a2e5bda488a75fe973fa302203f79..e5051d45956f31dae26c9b925e795b998ed60625 100644 (file)
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -1135,6 +1135,8 @@
 
 #endif /* CONFIG_405EZ */
 
+#define GPIO0_BASE             GPIO_BASE
+
 #if defined(CONFIG_405EX)
 #define SDR0_SRST              0x0200
 

diff --git a/include/ppc440.h b/include/ppc440.h
index 2f841fa6bc66ab9a40b92515b3cdfb73492f8a29..dfa3d2a6100e980327dab074e21c65d98c5e869b 100644 (file)
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -3187,9 +3187,6 @@
 /******************************************************************************
  * GPIO macro register defines
  ******************************************************************************/
-#define GPIO0                  0
-#define GPIO1                  1
-
 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
@@ -3205,31 +3202,6 @@
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
 #define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
 
-/* Offsets */
-#define GPIOx_OR    0x00       /* GPIO Output Register */
-#define GPIOx_TCR   0x04       /* GPIO Three-State Control Register */
-#define GPIOx_OSL   0x08       /* GPIO Output Select Register (Bits 0-31) */
-#define GPIOx_OSH   0x0C       /* GPIO Ouput Select Register (Bits 32-63) */
-#define GPIOx_TSL   0x10       /* GPIO Three-State Select Register (Bits 0-31) */
-#define GPIOx_TSH   0x14       /* GPIO Three-State Select Register  (Bits 32-63) */
-#define GPIOx_ODR   0x18       /* GPIO Open drain Register */
-#define GPIOx_IR    0x1C       /* GPIO Input Register */
-#define GPIOx_RR1   0x20       /* GPIO Receive Register 1 */
-#define GPIOx_RR2   0x24       /* GPIO Receive Register 2 */
-#define GPIOx_RR3   0x28       /* GPIO Receive Register 3 */
-#define GPIOx_IS1L  0x30       /* GPIO Input Select Register 1 (Bits 0-31) */
-#define GPIOx_IS1H  0x34       /* GPIO Input Select Register 1 (Bits 32-63) */
-#define GPIOx_IS2L  0x38       /* GPIO Input Select Register 2 (Bits 0-31) */
-#define GPIOx_IS2H  0x3C       /* GPIO Input Select Register 2 (Bits 32-63) */
-#define GPIOx_IS3L  0x40       /* GPIO Input Select Register 3 (Bits 0-31) */
-#define GPIOx_IS3H  0x44       /* GPIO Input Select Register 3 (Bits 32-63) */
-
-#define GPIO_OS(x)     (x+GPIOx_OSL)   /* GPIO Output Register High or Low */
-#define GPIO_TS(x)     (x+GPIOx_TSL)   /* GPIO Three-state Control Reg High or Low */
-#define GPIO_IS1(x)    (x+GPIOx_IS1L)  /* GPIO Input register1 High or Low */
-#define GPIO_IS2(x)    (x+GPIOx_IS2L)  /* GPIO Input register2 High or Low */
-#define GPIO_IS3(x)    (x+GPIOx_IS3L)  /* GPIO Input register3 High or Low */
-
 #define GPIO0_OR               (GPIO0_BASE+0x0)
 #define GPIO0_TCR              (GPIO0_BASE+0x4)
 #define GPIO0_OSRL             (GPIO0_BASE+0x8)