Changes for U-Boot 1.0.2:
======================================================================
+* Patch by Stephan Linz, 09 Mar 2004
+ - Add support for the SSV ADNP/ESC1 (Nios Softcore)
+
+* Patch by George G. Davis, 9 Mar 2004:
+ fix recent build failure for SA1100 target
+
+* Patch by Travis Sawyer, 09 Mar 2004:
+ Support native interrupt mode for the IBM440GX.
+ Previously it was running in 440GP compatibility mode.
+
* Patch by Philippe Robin, 09 Mar 2004:
Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
Platform support.
N: Stephan Linz
E: linz@li-pro.net
D: Support for Nios Stratix Development Kit (DK-1S10)
+D: Support for SSV ADNP/ESC1 (Nios Cyclone)
W: http://www.li-pro.net
N: Raymond Lo
Stephan Linz <linz@li-pro.net>
DK1S10 Nios-32
+ ADNPESC1 Nios-32
Scott McNutt <smcnutt@psyent.com>
#########################################################################
LIST_nios=" \
+ ADNPESC1 ADNPESC1_base_32 \
+ ADNPESC1_DNPEVA2_base_32 \
DK1C20 DK1C20_standard_32 \
DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
"
}
@./mkconfig -a DK1S10 nios nios dk1s10 altera
+ADNPESC1_DNPEVA2_base_32_config \
+ADNPESC1_base_32_config \
+ADNPESC1_config: unconfig
+ @ >include/config.h
+ @[ -z "$(findstring _DNPEVA2,$@)" ] || \
+ { echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \
+ echo "... DNP/EVA2 configuration" ; \
+ }
+ @[ -z "$(findstring _base_32,$@)" ] || \
+ { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
+ echo "... NIOS 'base_32' configuration" ; \
+ }
+ @[ -z "$(findstring ADNPESC1_config,$@)" ] || \
+ { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
+ echo "... NIOS 'base_32' configuration (DEFAULT)" ; \
+ }
+ @./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv
+
#########################################################################
## MIPS32 AU1X00
--- /dev/null
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o flash.o misc.o
+
+SOBJS = vectors.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nios-io.h>
+#include <spi.h>
+
+#if defined(CONFIG_HW_WATCHDOG)
+extern void ssv_wd_pio_init(void); /* comes from ../common/wd_pio.c
+ included by ./misc.c */
+#endif
+
+void _default_hdlr (void)
+{
+ printf ("default_hdlr\n");
+}
+
+int board_early_init_f (void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ ssv_wd_pio_init();
+#endif
+ return 0;
+}
+
+int checkboard (void)
+{
+ puts ( "Board: SSV DilNetPC ADNP/ESC1"
+#if defined(CONFIG_DNPEVA2)
+ " on DNP/EVA2"
+#endif
+ "\n");
+#if defined(CONFIG_NIOS_BASE_32)
+ puts ("Conf.: SSV Base 32 (nios_32)\n");
+#endif
+
+ return 0;
+}
+
+long int initdram (int board_type)
+{
+ return (0);
+}
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) && CONFIG_NIOS_SPI
+
+#define SPI_RTC_CS_MASK 0x00000001
+
+void spi_rtc_chipsel(int cs)
+{
+ nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
+
+ if (cs)
+ spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */
+ else
+ spi->slaveselect = 0; /* deactivate (0) */
+}
+
+/*
+ * The SPI command uses this table of functions for controlling the SPI
+ * chip selects: it calls the appropriate function to control the SPI
+ * chip selects.
+ */
+spi_chipsel_type spi_chipsel[] = {
+ spi_rtc_chipsel
+};
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
+#endif /* CFG_CMD_SPI */
+
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return 0; /* No hotkeys supported */
+}
+#endif /* CONFIG_POST */
--- /dev/null
+#
+# (C) Copyright 2004
+# Li-Pro.Net <www.li-pro.net>
+# Stephan Linz <linz@li-pro.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x02fc0000 # ATTENTION: notice your CFG_MONITOR_LEN setting
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+/*
+ * include common flash code (for ssv boards)
+ */
+#include "../common/flash.c"
+
+/*---------------------------------------------------------------------*/
+#define BANKSZ (8 * 1024 * 1024)
+#define SECTSZ (64 * 1024)
+#define UBOOTSECS ((CFG_MONITOR_LEN + CFG_ENV_SIZE) / SECTSZ)
+#define UBOOTAREA (UBOOTSECS * 64 * 1024) /* monitor / env area */
+
+/*---------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+ int i;
+ unsigned long addr;
+ flash_info_t *fli = &flash_info[0];
+
+ fli->size = BANKSZ;
+ fli->sector_count = CFG_MAX_FLASH_SECT;
+ fli->flash_id = FLASH_MAN_AMD + FLASH_AMLV640U;
+
+ addr = CFG_FLASH_BASE;
+ for (i = 0; i < fli->sector_count; ++i) {
+ fli->start[i] = addr;
+ addr += SECTSZ;
+
+ /* Protect monitor / environment area */
+ if (addr <= (CFG_FLASH_BASE + UBOOTAREA))
+ fli->protect[i] = 1;
+ else
+ fli->protect[i] = 0;
+ }
+
+ return (BANKSZ);
+}
--- /dev/null
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * board/ssv/adnpesc1/misc.c
+ *
+ * miscellaneous board interfaces / drivers
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_STATUS_LED)
+#include "../common/cmd_sled.c"
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG)
+#include "../common/wd_pio.c"
+#endif
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+#include "../common/post.c"
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-nios")
+OUTPUT_ARCH(nios)
+ENTRY(_start)
+
+SECTIONS
+{
+ .text :
+ {
+ cpu/nios/start.o (.text)
+ *(.text)
+ }
+ __text_end = .;
+
+ . = ALIGN(4);
+ .rodata :
+ {
+ *(.rodata)
+ }
+ __rodata_end = .;
+
+ . = ALIGN(4);
+ .data :
+ {
+ *(.data)
+ }
+ . = ALIGN(4);
+ __data_end = .;
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ }
+ . = ALIGN(4);
+ __u_boot_cmd_end = .;
+
+ __bss_start = .;
+ . = ALIGN(4);
+ .bss :
+ {
+ *(.bss)
+ }
+ . = ALIGN(4);
+ __bss_end = .;
+}
--- /dev/null
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+
+/*************************************************************************
+ * Exception Vector Table
+ *
+ * This could have gone in the cpu soure tree, but the whole point of
+ * Nios is customization -- and polluting the cpu source tree with
+ * board-specific ifdef's really defeats the purpose, no? With this in
+ * the board-specific tree, each board has the freedom to organize
+ * vectors/traps, etc anyway it wants. The init code copies this table
+ * to the proper location.
+ *
+ * Each board can do what it likes here. But there are four "standard"
+ * handlers availble:
+ *
+ * _cwp_lolimit -Handles register window underflows.
+ * _cwp_hilimit -Handles register window overflows.
+ * _timebase_int -Increments the timebase.
+ * _def_xhandler -Default exception handler.
+ *
+ * _timebase_int handles a Nios Timer interrupt and increments the
+ * timestamp used for the get_timer(), reset_timer(), etc. routines. It
+ * expects the timer to be configured like the standard-32 low priority
+ * timer.
+ *
+ * _def_xhandler dispatches exceptions/traps via the external_interrupt()
+ * routine. This lets you use the irq_install_handler() and handle your
+ * interrupts/traps with code written in C.
+ ************************************************************************/
+
+ .data
+ .global _vectors
+ .align 4
+_vectors:
+
+#if defined(CFG_NIOS_CPU_OCI_BASE)
+ /* OCI does the reset job */
+ .long _def_xhandler@h /* Vector 0 - NMI / Reset */
+#else
+ /* there is no OCI, so we have to do a direct reset jump here */
+ .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */
+#endif
+ .long _cwp_lolimit@h /* Vector 1 - underflow */
+ .long _cwp_hilimit@h /* Vector 2 - overflow */
+
+ .long _def_xhandler@h /* Vector 3 - GNUPro debug */
+ .long _def_xhandler@h /* Vector 4 - GNUPro debug */
+ .long _def_xhandler@h /* Vector 5 - GNUPro debug */
+ .long _def_xhandler@h /* Vector 6 - future reserved */
+ .long _def_xhandler@h /* Vector 7 - future reserved */
+ .long _def_xhandler@h /* Vector 8 - future reserved */
+ .long _def_xhandler@h /* Vector 9 - future reserved */
+ .long _def_xhandler@h /* Vector 10 - future reserved */
+ .long _def_xhandler@h /* Vector 11 - future reserved */
+ .long _def_xhandler@h /* Vector 12 - future reserved */
+ .long _def_xhandler@h /* Vector 13 - future reserved */
+ .long _def_xhandler@h /* Vector 14 - future reserved */
+ .long _def_xhandler@h /* Vector 15 - future reserved */
+#if (CFG_NIOS_TMRIRQ == 16)
+ .long _timebase_int@h /* Vector 16 - lopri timer*/
+#else
+ .long _def_xhandler@h /* Vector 16 */
+#endif
+ .long _def_xhandler@h /* Vector 17 */
+ .long _def_xhandler@h /* Vector 18 */
+ .long _def_xhandler@h /* Vector 19 */
+ .long _def_xhandler@h /* Vector 20 */
+ .long _def_xhandler@h /* Vector 21 */
+ .long _def_xhandler@h /* Vector 22 */
+ .long _def_xhandler@h /* Vector 23 */
+ .long _def_xhandler@h /* Vector 24 */
+ .long _def_xhandler@h /* Vector 25 */
+ .long _def_xhandler@h /* Vector 26 */
+ .long _def_xhandler@h /* Vector 27 */
+ .long _def_xhandler@h /* Vector 28 */
+ .long _def_xhandler@h /* Vector 29 */
+ .long _def_xhandler@h /* Vector 30 */
+ .long _def_xhandler@h /* Vector 31 */
+ .long _def_xhandler@h /* Vector 32 */
+ .long _def_xhandler@h /* Vector 33 */
+ .long _def_xhandler@h /* Vector 34 */
+ .long _def_xhandler@h /* Vector 35 */
+ .long _def_xhandler@h /* Vector 36 */
+ .long _def_xhandler@h /* Vector 37 */
+ .long _def_xhandler@h /* Vector 38 */
+ .long _def_xhandler@h /* Vector 39 */
+ .long _def_xhandler@h /* Vector 40 */
+ .long _def_xhandler@h /* Vector 41 */
+ .long _def_xhandler@h /* Vector 42 */
+ .long _def_xhandler@h /* Vector 43 */
+ .long _def_xhandler@h /* Vector 44 */
+ .long _def_xhandler@h /* Vector 45 */
+ .long _def_xhandler@h /* Vector 46 */
+ .long _def_xhandler@h /* Vector 47 */
+ .long _def_xhandler@h /* Vector 48 */
+ .long _def_xhandler@h /* Vector 49 */
+#if (CFG_NIOS_TMRIRQ == 50)
+ .long _timebase_int@h /* Vector 50 - lopri timer*/
+#else
+ .long _def_xhandler@h /* Vector 50 */
+#endif
+ .long _def_xhandler@h /* Vector 51 */
+ .long _def_xhandler@h /* Vector 52 */
+ .long _def_xhandler@h /* Vector 53 */
+ .long _def_xhandler@h /* Vector 54 */
+ .long _def_xhandler@h /* Vector 55 */
+ .long _def_xhandler@h /* Vector 56 */
+ .long _def_xhandler@h /* Vector 57 */
+ .long _def_xhandler@h /* Vector 58 */
+ .long _def_xhandler@h /* Vector 59 */
+ .long _def_xhandler@h /* Vector 60 */
+ .long _def_xhandler@h /* Vector 61 */
+ .long _def_xhandler@h /* Vector 62 */
+ .long _def_xhandler@h /* Vector 63 */
--- /dev/null
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <status_led.h>
+
+#if defined(CONFIG_STATUS_LED)
+
+/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+ * !!!!! Q u i c k & D i r t y H a c k !!!!!
+ * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+ * !!!!! !!!!!
+ * !!!!! Next type definition was coming from original !!!!!
+ * !!!!! status LED driver drivers/status_led.c and !!!!!
+ * !!!!! should exported for using here. !!!!!
+ * !!!!! !!!!!
+ * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
+
+typedef struct {
+ led_id_t mask;
+ int state;
+ int period;
+ int cnt;
+} led_dev_t;
+
+extern led_dev_t led_dev[];
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int led_id = 0;
+
+ if (argc > 1) {
+#ifdef STATUS_LED_BOOT
+ if (!strcmp (argv[1], "boot")) {
+ led_id = STATUS_LED_BOOT + 1;
+ }
+#endif
+#ifdef STATUS_LED_RED
+ if (!strcmp (argv[1], "red")) {
+ led_id = STATUS_LED_RED + 1;
+ }
+#endif
+#ifdef STATUS_LED_YELLOW
+ if (!strcmp (argv[1], "yellow")) {
+ led_id = STATUS_LED_YELLOW + 1;
+ }
+#endif
+#ifdef STATUS_LED_GREEN
+ if (!strcmp (argv[1], "green")) {
+ led_id = STATUS_LED_GREEN + 1;
+ }
+#endif
+ }
+
+ switch (argc) {
+ case 1:
+#if (STATUS_LED_BITS > 3)
+ for (; led_id < 4; led_id++)
+#elif (STATUS_LED_BITS > 2)
+ for (; led_id < 3; led_id++)
+#elif (STATUS_LED_BITS > 1)
+ for (; led_id < 2; led_id++)
+#elif (STATUS_LED_BITS > 0)
+ for (; led_id < 1; led_id++)
+#else
+#error "*** STATUS_LED_BITS not correct defined ***"
+#endif
+ {
+ printf ("Status LED '%s' is %s\n",
+ led_id == STATUS_LED_BOOT ? "boot"
+ : led_id == STATUS_LED_RED ? "red"
+ : led_id == STATUS_LED_YELLOW ? "yellow"
+ : led_id ==
+ STATUS_LED_GREEN ? "green" : "unknown",
+ led_dev[led_id].state ==
+ STATUS_LED_ON ? "on" : led_dev[led_id].
+ state ==
+ STATUS_LED_OFF ? "off" : led_dev[led_id].
+ state ==
+ STATUS_LED_BLINKING ? "blinking" : "unknown");
+ }
+ return 0;
+ case 2:
+ if (led_id) {
+ printf ("Status LED '%s' is %s\n", argv[1],
+ led_dev[led_id - 1].state ==
+ STATUS_LED_ON ? "on" : led_dev[led_id -
+ 1].state ==
+ STATUS_LED_OFF ? "off" : led_dev[led_id -
+ 1].state ==
+ STATUS_LED_BLINKING ? "blinking" : "unknown");
+ return 0;
+ } else
+ break;
+ case 3:
+ if (led_id) {
+ if (!strcmp (argv[2], "on")) {
+ status_led_set (led_id - 1, STATUS_LED_ON);
+ return 0;
+ } else if (!strcmp (argv[2], "off")) {
+ status_led_set (led_id - 1, STATUS_LED_OFF);
+ return 0;
+ } else if (!strcmp (argv[2], "blink")) {
+ status_led_set (led_id - 1,
+ STATUS_LED_BLINKING);
+ return 0;
+ } else
+ break;
+ } else
+ break;
+ default:
+ break;
+ }
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+}
+
+#ifdef STATUS_LED_BOOT
+#ifdef STATUS_LED_RED
+#ifdef STATUS_LED_YELLOW
+#ifdef STATUS_LED_GREEN
+#define __NAME_STR " - name: boot|red|yellow|green\n"
+#else
+#define __NAME_STR " - name: boot|red|yellow\n"
+#endif
+#else
+#define __NAME_STR " - name: boot|red\n"
+#endif
+#else
+#define __NAME_STR " - name: boot\n"
+#endif
+#else
+#define __NAME_STR " - name: (no such defined)\n"
+#endif
+
+U_BOOT_CMD (sled, 3, 0, do_sled,
+ "sled - check and set status led\n",
+ "sled [name [state]]\n" __NAME_STR " - state: on|off|blink\n");
+#endif /* CFG_CMD_BSP */
+#endif /* CONFIG_STATUS_LED */
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <watchdog.h>
+#include <nios.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+ int i, k;
+ unsigned long size;
+ int erased;
+ volatile unsigned char *flash;
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+
+ /* Check if whole sector is erased */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned char *) info->start[i];
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ /* Print the info */
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s%s", info->start[i], erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+ }
+ printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int prot, sect, wait;
+ unsigned oldpri;
+ ulong start;
+
+ /* Some sanity checking */
+ if ((s_first < 0) || (s_first > s_last)) {
+ printf ("- no sectors to erase\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+#ifdef DEBUG
+ for (sect = s_first; sect <= s_last; sect++) {
+ printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]);
+ }
+#endif
+
+ /* NOTE: disabling interrupts on Nios can be very bad since it
+ * also disables the LO_LIMIT exception. It's better here to
+ * set the interrupt priority to 3 & restore it when we're done.
+ */
+ oldpri = ipri (3);
+
+ /* It's ok to erase multiple sectors provided we don't delay more
+ * than 50 usec between cmds ... at which point the erase time-out
+ * occurs. So don't go and put printf() calls in the loop ... it
+ * won't be very helpful ;-)
+ */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+ *addr = 0xf0;
+ *(addr+0xAAA/2) = 0xaa;
+ *(addr+0x554/2) = 0x55;
+ *(addr+0xAAA/2) = 0x80;
+ *(addr+0xAAA/2) = 0xaa;
+ *(addr+0x554/2) = 0x55;
+ *addr2 = 0x30;
+ /* Now just wait for 0xffff & provide some user
+ * feedback while we wait. Here we have to grant
+ * timer interrupts. Otherwise get_timer() can't
+ * work right. */
+ ipri(oldpri);
+ start = get_timer (0);
+ while (*addr2 != 0xffff) {
+ for (wait = 8; wait; wait--) {
+ udelay (125 * 1000);
+ }
+ putc ('.');
+ if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+ printf ("timeout\n");
+ return 1;
+ }
+ }
+ oldpri = ipri (3); /* disallow non important irqs again */
+ }
+ }
+
+ printf ("\n");
+ *addr = 0xf0;
+
+ /* Restore interrupt priority */
+ ipri (oldpri);
+
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * srcbuffer, ulong addr, ulong cnt)
+{
+
+ volatile CFG_FLASH_WORD_SIZE *cmd = (vu_short *) info->start[0];
+ volatile CFG_FLASH_WORD_SIZE *dst = (vu_short *) addr;
+ CFG_FLASH_WORD_SIZE *src = (void *) srcbuffer;
+ CFG_FLASH_WORD_SIZE b;
+ unsigned oldpri;
+ ulong start;
+
+ cnt /= sizeof(CFG_FLASH_WORD_SIZE);
+ while (cnt) {
+ /* Check for sufficient erase */
+ b = *src;
+ if ((*dst & b) != b) {
+ printf ("%02x : %02x\n", *dst, b);
+ return (2);
+ }
+
+ /* Disable interrupts other than window underflow
+ * (interrupt priority 2)
+ */
+ oldpri = ipri (3);
+ *(cmd+0xAAA/2) = 0xaa;
+ *(cmd+0x554/2) = 0x55;
+ *(cmd+0xAAA/2) = 0xa0;
+ ipri (oldpri);
+ *dst = b;
+
+ /* Verify write */
+ start = get_timer (0);
+ while (*dst != b) {
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ *cmd = 0xf0;
+ return 1;
+ }
+ }
+ dst++;
+ src++;
+ cnt--;
+ }
+
+ *cmd = 0xf0;
+ return (0);
+}
--- /dev/null
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+#if !defined(CFG_NIOS_POST_WORD_ADDR)
+#error "*** CFG_NIOS_POST_WORD_ADDR not defined ***"
+#endif
+
+void post_word_store (ulong a)
+{
+ volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR);
+ *(volatile ulong *) save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+ volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR);
+ return *(volatile ulong *) save_addr;
+}
+
+#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
--- /dev/null
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <nios.h>
+#include <nios-io.h>
+
+#if defined(CONFIG_HW_WATCHDOG)
+
+#if !defined(CONFIG_HW_WDENA_BASE)
+#error "*** CONFIG_HW_WDENA_BASE not defined ***"
+#if !defined(CONFIG_HW_WDENA_BIT)
+#error "*** CONFIG_HW_WDENA_BIT not defined ***"
+#endif
+#endif
+
+#if !defined(CONFIG_HW_WDTOG_BASE)
+#error "*** CONFIG_HW_WDTOG_BASE not defined ***"
+#if !defined(CONFIG_HW_WDTOG_BIT)
+#error "*** CONFIG_HW_WDTOG_BIT not defined ***"
+#endif
+#endif
+
+#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */
+static unsigned __wd_ena_pio_portval = 0;
+#endif
+
+#define WD_PIO_INIT_DONE(V) ((V) & (1 << CONFIG_HW_WDENA_BIT))
+
+void ssv_wd_pio_init(void)
+{
+ nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
+ nios_pio_t *trg_piop = (nios_pio_t*)CONFIG_HW_WDTOG_BASE;
+
+ trg_piop->data &= ~(1 << CONFIG_HW_WDTOG_BIT);
+
+#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */
+
+ __wd_ena_pio_portval |= (1 << CONFIG_HW_WDENA_BIT);
+ ena_piop->data = __wd_ena_pio_portval;
+
+#else /* !CONFIG_HW_WDPORT_WRONLY */
+
+ trg_piop->direction |= (1 << CONFIG_HW_WDTOG_BIT);
+
+ ena_piop->data |= (1 << CONFIG_HW_WDENA_BIT);
+ ena_piop->direction |= (1 << CONFIG_HW_WDENA_BIT);
+
+#endif /* CONFIG_HW_WDPORT_WRONLY */
+}
+
+void ssv_wd_pio_done(void)
+{
+ nios_pio_t *piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
+
+#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */
+
+ __wd_ena_pio_portval &= ~(1 << CONFIG_HW_WDENA_BIT);
+ piop->data = __wd_ena_pio_portval;
+
+#else /* !CONFIG_HW_WDPORT_WRONLY */
+
+ piop->data &= ~(1 << CONFIG_HW_WDENA_BIT);
+
+#endif /* CONFIG_HW_WDPORT_WRONLY */
+}
+
+void ssv_wd_pio_reset(void)
+{
+ nios_pio_t *trg_piop = (nios_pio_t*)CONFIG_HW_WDTOG_BASE;
+
+#ifdef CONFIG_HW_WDPORT_WRONLY
+ if (WD_PIO_INIT_DONE(__wd_ena_pio_portval))
+#else
+ nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
+
+ if (WD_PIO_INIT_DONE(ena_piop->data))
+#endif
+ {
+ trg_piop->data |= (1 << CONFIG_HW_WDTOG_BIT);
+ trg_piop->data &= ~(1 << CONFIG_HW_WDTOG_BIT);
+ }
+}
+
+void hw_watchdog_reset(void)
+{
+ int re_enable = disable_interrupts ();
+
+ ssv_wd_pio_reset();
+ if (re_enable)
+ enable_interrupts ();
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
+
+ switch (argc)
+ {
+ case 1:
+ printf ("Watchdog timer status is %s\n",
+#ifdef CONFIG_HW_WDPORT_WRONLY
+ WD_PIO_INIT_DONE(__wd_ena_pio_portval)
+#else
+ WD_PIO_INIT_DONE(ena_piop->data)
+#endif
+ ? "on" : "off");
+ return 0;
+ case 2:
+ if (!strcmp(argv[1],"on"))
+ {
+ ssv_wd_pio_init();
+ printf("Watchdog timer now is on\n");
+ return 0;
+ }
+ else if (!strcmp(argv[1],"off"))
+ {
+ ssv_wd_pio_done();
+ printf("Watchdog timer now is off\n");
+ return 0;
+ }
+ break;
+ default:
+ break;
+ }
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ wd, 2, 1, do_wd,
+ "wd - check and set watchdog\n",
+ "on - switch watchDog on\n"
+ "wd off - switch watchdog off\n"
+ "wd - print current status\n"
+);
+#endif /* CFG_CMD_BSP */
+#endif /* CONFIG_HW_WATCHDOG */
#endif
#if defined(CONFIG_440_GX)
+ /* Take the GX out of compatibility mode
+ * Travis Sawyer, 9 Mar 2004
+ * NOTE: 440gx user manual inconsistency here
+ * Compatibility mode and Ethernet Clock select are not
+ * correct in the manual
+ */
+ mfsdr(sdr_mfr, val);
+ val &= ~0x10000000;
+ mtsdr(sdr_mfr,val);
+
/* Enable UIC interrupts via UIC Base Enable Register */
- mtdcr(uicb0er, UICB0_ALL);
- mtdcr(uicb0cr, UICB0_ALL);
+ mtdcr(uicb0sr, UICB0_ALL);
+ mtdcr(uicb0er, 0x54000000);
+ /* None are critical */
+ mtdcr(uicb0cr, 0);
#endif
return (0);
/* 440 GX uses base uic register */
uic_msr = mfdcr(uicb0msr);
- uic0_interrupt(0);
- uic1_interrupt(0);
- uic2_interrupt(0);
+ if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) )
+ uic0_interrupt(0);
- mtdcr(uicb0sr, UICB0_ALL);
+ if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
+ uic1_interrupt(0);
+
+ if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
+ uic2_interrupt(0);
+
+ mtdcr(uicb0sr, uic_msr);
return;
while (tmo >= get_timer_masked ())
/*NOP*/;
}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CFG_HZ;
+ return tbclk;
+}
--- /dev/null
+
+ SSV ADNP/ESC1 Embedded Softcore Computing
+ Nios Softcore, Altera Cyclone FPGA
+
+ Last Update: February 27, 2004
+====================================================================
+
+This file contains information regarding U-Boot and the SSV Embedded
+Nios Softcore Computing platform ADNP/ESC1. For general Nios
+information see doc/README.nios.
+
+Most stuff of this file was borrowed and based on README.dk1s10,
+the Altera DK-1S10 related information file.
+
+For those interested in contributing ... see HELP WANTED section
+in doc/README.nios.
+
+Contents:
+
+ 1. Files
+ 2. Memory Organization
+ 3. CPU Variations
+ 4. Examples
+ 5. Programming U-Boot into FLASH with GERMS
+ 6. Autoboot
+ 7. U-Boot environment convention and update philosophy
+
+====================================================================
+
+1. Files
+=========
+ board/ssv/adnpesc1/*
+ include/configs/ADNPESC1.h
+ include/configs/ADNPESC1_base_32.h
+
+
+2. Memory Organization
+=======================
+
+For the most part, you can put things pretty much anywhere.
+This is pretty flexible for Nios. So here we make some arbitrary
+choices & assume that the monitor is placed at the end of a memory
+resource. So you must make sure TEXT_BASE is chosen appropriately.
+This is very important if you plan to move your memory to another
+place as configured at this time!
+
+ -The heap is placed below the monitor (U-Boot code).
+ -Global data is placed below the heap.
+ -The stack is placed below global data (&grows down).
+
+(see doc/README.adnpesc1_base32 too)
+
+
+3. CPU Variations
+=================
+
+There are more than one NIOS CPU variation for the ADNP/ESC1 possible.
+U-Boot supports the following CPU configurations:
+
+ - SSV Basis 32 (make ADNPESC1_base_32_config)
+ - SSV Basis 32 at DNP evaluation base board 2
+ (make ADNPESC1_DNPEVA2_base_32_config)
+
+
+4. Examples
+============
+
+The hello_world example works fine. To try out you have to change
+the default load address from 0x0100_0000 to 0x0204_0000 in
+examples/Makefile (the real SDRAM for default board configuration).
+
+
+5. Programming U-Boot into FLASH with GERMS
+============================================
+
+The current version of the ADNP/ESC1 port with the default
+configuration settings occupies about 97 KBytes of flash.
+A minimal configuration occupies less than 70 KByte
+(network, SPI, POST and board command support disabled). You
+can save more memory by deactivating the Hu-Shell support and
+long command help (CFG_HUSH_PARSER, CFG_LONGHELP).
+
+To program U-Boot into the ADNP/ESC1 flash using GERMS do the
+following:
+
+1. Download U-Boot to its target run space in SDRAM:
+
+ a. Close jumper RCM_EN# and push the reset button.
+
+ b. From the command line, download U-Boot using the
+ nios-run:
+
+ $ nios-run -r u-boot.srec
+
+ NOTE: In some cases this want fail. I don't know why,
+ but try again.
+
+This takes about 1 minute (GERMS is not very speedy here).
+After u-boot is downloaded it will be executed. You should
+see the following:
+
+ U-Boot 1.0.2 (Jan 30 2004 - 12:59:15)
+
+ CPU: Nios-32 Rev. 3.3 (0x3038)
+ Reg file size: 512 LO_LIMIT/HI_LIMIT: 1/30
+ Board: SSV DilNetPC ADNP/ESC1
+ Conf.: SSV Base 32 (nios_32)
+ In: serial
+ Out: serial
+ Err: serial
+ ADNPESC1 >
+
+
+2. Quit nios-run and start your terminal application (e.g. start
+ Hyperterminal or minicom).
+
+3. Download the u-boot code to RAM. When using Hyperterminal, do the
+ following:
+
+ a. From the u-boot command prompt start a binary download to SDRAM:
+
+ at the SSV Basis 32 to SDRAM:
+
+ ==> loadb 2000100
+
+ b. Download u-boot.bin using kermit.
+
+4. From the U-Boot command prompt, erase flash:
+
+ at the SSV Basis 32 from 0x1000000 to 0x103ffff:
+
+ ==> protect off 1:0-3
+ ==> erase 1:0-3
+
+5. Copy the binary image from SDRAM to flash:
+
+ at the SSV Basis 32 from SDRAM:
+
+ ==> cp.b 2000100 1000000 $filesize
+
+U-Boot will now automatically start when the board is powered on or
+reset using the SSV Basis 32 configuration without closed RCM jumper.
+To start U-Boot with closed RCM Jumper, enter the following GERMS
+command:
+
+ + g 1000000
+
+
+6. Autoboot
+===========
+
+U-Boot will try to boot a valid Nios application from Flash. For this
+it will use the deposited Hu-Shell script in environment variable
+'bootcmd' which is looking for a valid Nios application identifier
+string in Flash and go on at even its entry address. For more
+information see the next chapter.
+
+
+7. U-Boot environment convention and update philosophy
+======================================================
+
+U-Boot for the SSV ADNP/ESC1 target knows about many environment
+variables used to control the startup process, update process for
+raw Nios applications, and optionally file system image updates.
+In default configuration there are two Hu-Shell scripts to update
+the Nios application and/or the file system image:
+
+1. Update Nios application (ex. the uCLinux kernel):
+
+ run 'appl_update'
+
+2. Update optional file system image (ex. RomFS image used by uCLinux):
+
+ run 'fs_update'
+
+The Nios application can be any programm code generated in relation
+to the Nios application identifier -- the string "Nios" at offset
+address 0x0c. To use the scripts like described above in a secure way
+you have to check-up the next environment variables:
+
+1. update_allowed
+
+ - Update switch -- must be set to '1' (one) to allow any update
+ - default is '0' (zero)
+
+ NOTE: You should avoid to save this variable with non zero
+ value to Flash. Otherwise it would be allow any
+ update process at any time!
+
+2. appl_entry_addr
+
+ - Nios application area start address (usually in Flash)
+ - this is the startup address for autoboot
+ - each Nios application code we want to update will be copied
+ to this address
+ - default is CFG_ADNPESC1_NIOS_APPL_ENTRY
+
+3. appl_end_addr
+
+ - Nios application area end address (usually in Flash)
+ - will be used to unprotect/erase the Flash area while updating
+ - default is CFG_ADNPESC1_NIOS_APPL_END
+
+4. appl_ident_addr
+
+ - address of the Nios application identification string
+ - this is the address checked-up by autoboot
+ - default is CFG_ADNPESC1_NIOS_APPL_IDENT
+
+5. appl_ident_str
+
+ - the Nios application identification string itself
+ - default is CFG_ADNPESC1_NIOS_IDENTIFIER
+
+6. appl_name
+
+ - name of file we have to download/update
+ - default is ADNPESC1/base32/linux.bin
+
+7. fs_base_addr
+
+ - optionally file system area start address (usually in Flash)
+ - each file system we want to update will be copied to this address
+ - default is CFG_ADNPESC1_FILESYSTEM_BASE
+
+8. fs_end_addr
+
+ - optionally file system area end address (usually in Flash)
+ - will be used to unprotect/erase the Flash area while updating
+ - default is CFG_ADNPESC1_FILESYSTEM_END
+
+9. fs_name
+
+ - name of file we have to download/update
+ - default is ADNPESC1/base32/romfs.img
--- /dev/null
+
+TODO: specify IDE i/f
+
+
+===============================================================================
+ C P U , M E M O R Y , I N / O U T C O M P O N E N T S
+===============================================================================
+see also [1]-[5]
+
+CPU: "DNP_ESC1"
+ 32 bit NIOS for 50 MHz
+ 512 Byte for register file (30 levels)
+ with out instruction cache
+ with out data cache
+ 2 KByte On Chip ROM with GERMS boot monitor
+ with out On Chip RAM
+ MSTEP multiplier
+ no Debug Core
+ no On Chip Instrumentation (OCI)
+
+ U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
+ CFG_NIOS_CPU_ICACHE = (not present)
+ CFG_NIOS_CPU_DCACHE = (not present)
+ CFG_NIOS_CPU_REG_NUMS = 512
+ CFG_NIOS_CPU_MUL = 0
+ CFG_NIOS_CPU_MSTEP = 1
+ CFG_NIOS_CPU_DBG_CORE = 0
+
+IRQ: Nr. | used by
+ ------+--------------------------------------------------------
+ 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
+ 17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17
+ 18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18
+ 20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ =
+ | PIO6 | CFG_NIOS_CPU_PIO6_IRQ = 20
+ 25 | SPI0 | CFG_NIOS_CPU_SPI0_IRQ = 25
+ 31 | PIO7 | CFG_NIOS_CPU_PIO7_IRQ = 31
+ 32 | PIO8 | CFG_NIOS_CPU_PIO8_IRQ = 32
+ 33 | PIO9 | CFG_NIOS_CPU_PIO9_IRQ = 33
+ 34 | PIO10 | CFG_NIOS_CPU_PIO10_IRQ = 34
+ 35 | PIO11 | CFG_NIOS_CPU_PIO11_IRQ = 35
+ 36 | PIO12 | CFG_NIOS_CPU_PIO12_IRQ =
+ | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 36
+ 37 | PIO13 | CFG_NIOS_CPU_PIO13_IRQ =
+ | IDE1 | CFG_NIOS_CPU_IDE1_IRQ = 37
+
+MEMORY: 8 MByte Flash
+ 16 MByte SDRAM
+
+Timer: TIMER0: high priority programmable timer (IRQ16)
+
+ U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0
+ CFG_NIOS_CPU_USER_TIMER = (not present)
+
+PIO: Nr. | description
+ ------+--------------------------------------------------------
+ PIO0 | PORTA: 8 in/outputs for general purpose usage
+ PIO1 | PORTB: 8 in/outputs for general purpose usage
+ PIO2 | PORTC: 4 in/outputs for general purpose usage
+ PIO3 | RCM: 1 input for RCM_EN# jumper (Req.Conf.Mon.)
+ PIO4 | WDTENA: 1 output to enable the on-board watchdog
+ PIO5 | WDTTRIG: 1 output to trigger the on-board watchdog
+ PIO6 | LAN0INT: 1 input for LAN91C111 irq input (IRQ20)
+ PIO7 | INT1: 1 input for general purpose irq (IRQ31)
+ PIO8 | INT2: 1 input for general purpose irq (IRQ32)
+ PIO9 | INT3: 1 input for general purpose irq (IRQ33)
+ PIO10| INT4: 1 input for general purpose irq (IRQ34)
+ PIO11| INT5: 1 input for general purpose irq (IRQ35)
+ PIO12| INT6: 1 input for general purpose irq (IRQ36)
+ | IDE0INT: (same) for IDE0 irq input
+ PIO13| INT7: 1 input for general purpose irq (IRQ37)
+ | IDE1INT: (same) for IDE1 irq input
+
+ U-Boot CFG: CFG_NIOS_CPU_PORTA_PIO = 0
+ CFG_NIOS_CPU_PORTB_PIO = 1
+ CFG_NIOS_CPU_PORTC_PIO = 2
+ CFG_NIOS_CPU_RCM_PIO = 3
+ CFG_NIOS_CPU_WDTENA_PIO = 4
+ CFG_NIOS_CPU_WDTTRIG_PIO = 5
+ CFG_NIOS_CPU_LED_PIO = (not present)
+
+UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, RTS/CTS (IRQ17)
+ UART1: fixed baudrate of 115200, fixed protocol 8N1,
+ without handshake RTS/CTS (IRQ18)
+
+SPI: SPI0: master capable, 1 slave selectable, 250kHz target clock,
+ 2 usec targets delay between slave select and clock,
+ data is transferred MSB-first / LSB-last (IRQ25)
+
+LAN: SMsC LAN91C111 with:
+ - without offset
+ - data bus width 16 bit (on-board hard wired at 32 bit bus)
+ - !!! 32 bit bus access --> each address * 2 !!!
+
+IDE: (TODO)
+
+
+===============================================================================
+ M E M O R Y M A P
+===============================================================================
+
+- - - - - - - - - - - external extension - - - - - - - - - - - - - - - - - - -
+
+ 0x44000000 ---32-----------16|15------------0-
+ | | | \
+ : (real size : : |
+ EXT3 (CS4) : and content : : > CFG_NIOS_CPU_CS3_SIZE
+ : unknown) : : | = 0x01000000
+ | | | /
+ 0x43000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS3_BASE
+ | | | \
+ : (real size : : |
+ EXT2 (CS3) : and content : : > CFG_NIOS_CPU_CS2_SIZE
+ : unknown) : : | = 0x01000000
+ | | | /
+ 0x42000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS2_BASE
+ | | | \
+ : (real size : : |
+ EXT1 (CS2) : and content : : > CFG_NIOS_CPU_CS1_SIZE
+ : unknown) : : | = 0x01000000
+ | | | /
+ 0x41000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS1_BASE
+ | | | \
+ : (real size : : |
+ EXT0 (CS1) : and content : : > CFG_NIOS_CPU_CS0_SIZE
+ : unknown) : : | = 0x01000000
+ | | | /
+ 0x40000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS0_BASE
+ | |
+ : gap :
+ : :
+
+- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
+
+ : :
+ : gap :
+ | |
+ 0x03000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK
+ | . | \
+ | . | | (U-Boot run-time system)
+ | . | |
+ | . | > CFG_MONITOR_LEN
+ | . | | = 0x00040000
+ | . | |
+ | . | /
+ 0x02fc0000 --+32-----------16|15------------0+ TEXT_BASE
+ | . | \
+ | . | > CFG_MALLOC_LEN (heap)
+ | . | /
+ --+32-----------16|15------------0+
+ | . | \
+ | . | > CFG_GBL_DATA_SIZE (global)
+ | . | /
+ --+32-----------16|15------------0+ CFG_INIT_SP (u-boot stack)
+ | . | \ \
+ | . | | |
+ | . | | > stack area
+ | . | | |
+ | . | | V
+ | . | |
+ | . | |
+ SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE
+ | . | | = 0x01000000
+ | . | |
+ 0x02000100 |- - - - - - - - - - - - - - - -+-|-
+ | . | | \
+ | . | | |
+ | . | | > CFG_NIOS_CPU_VEC_SIZE
+ | . | | | = 0x00000100
+ | | / /
+ 0x02000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE
+ 0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE
+ | | \
+ : gap : > (space for 2nd Flash)
+ | | /
+ 0x01800000 ---32-----------16|15------------0-
+ | sector 127 | \
+ + 0x7f0000 |- - - - - - - - - - - - - - - -| |
+ | : | |
+ Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
+ | sector 1 : | | = 0x00800000
+ + 0x010000 |- - - - - - - - - - - - - - - -| |
+ | sector 0 (size = 0x10000) | /
+ 0x01000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
+ | |
+ : gap :
+ : :
+
+- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
+
+ : :
+ : gap :
+ | |
+ 0x00010020 ---32-----------16|15------------0-
+ | | \
+ | register bank | |
+ | size = (real_size << 1) | |
+ | real_size = 0x10 | |
+ | +--------.---.---.--- | |
+ | | bank 0 \ 1 \ 2 \ 3 \ | |
+ | |---------------------------+ | |
+ LAN91C111 | | BANK | RESERVED | | > na_enet_size
+ | |- - - - - - -|- - - - - - -| | | = 0x00000020
+ | | RPCR | MIR | | |
+ | |- - - - - - -|- - - - - - -| | |
+ | | COUNTER | RCR | | |
+ | |- - - - - - -|- - - - - - -| | |
+ | | EPH STATUS | TCR | | |
+ | +---------------------------+ | /
+ 0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
+ | |
+ : gap :
+ : :
+
+- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
+
+ : :
+ : gap :
+ | |
+ 0x00001040 ---32-----------16|15------------0-
+ | | | \
+ : : : |
+ IDE1 i/f : : : > 0x00000020
+ [5] : : : |
+ | | | /
+ 0x00001020 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE1
+ | | | \
+ : : : |
+ IDE0 i/f : : : > 0x00000020
+ [5] : : : |
+ | | | /
+ 0x00001000 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
+ | |
+ : gap :
+ | |
+ 0x00000980 ---32-----------16|15------------0-
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO13 | interruptmask (1 bit) (rw) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x00000970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO13
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO12 | interruptmask (1 bit) (rw) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x00000960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO12
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO11 | interruptmask (1 bit) (rw) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x00000950 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO11
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO10 | interruptmask (1 bit) (rw) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x00000940 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO10
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO9 | interruptmask (1 bit) (rw) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x00000930 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO9
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO8 | interruptmask (1 bit) (rw) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x00000920 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO8
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO7 | interruptmask (1 bit) (rw) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x00000910 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO6 | interruptmask (1 bit) (rw) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
+ | |
+ : gap :
+ | |
+ 0x000008e0 ---32-----------16|15------------0-
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | endofpacket (16 bit) (rw) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | slaveselect (1 bit) (rw) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ SPI0 | (reserved) | |
+ [4] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
+ | control (11 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | status (9 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | txdata (16 bit) (wo) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | rxdata (16 bit) (ro) | /
+ 0x000008c0 ---32-----------16|15------------0- CFG_NIOS_CPU_SPI0
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO5 | (unused) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (wo) | /
+ 0x000008b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO4 | (unused) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (wo) | /
+ 0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO3 | (unused) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x00000890 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO2 | (unused) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (4 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (4 bit) (rw) | /
+ 0x00000880 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO1 | (unused) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (8 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (8 bit) (rw) | /
+ 0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO0 | (unused) | |
+ [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (8 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (8 bit) (rw) | /
+ 0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | snaph (16 bit) (rw) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ TIMER0 | snapl (16 bit) (rw) | |
+ [2] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
+ | periodh (16 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | periodl (16 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | control (4 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | status (2 bit) (rw) | /
+ 0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ UART1 | (unused) | > 0x00000020
+ [1] + 0x10 |- - - - - - - - - - - - - - - -| |
+ | control (10 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | status (10 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | txdata (8 bit) (wo) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | rxdata (8 bit) (ro) | /
+ 0x00000820 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ UART0 | (unused) | > 0x00000020
+ [1] + 0x10 |- - - - - - - - - - - - - - - -| |
+ | control (10 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | status (10 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | txdata (8 bit) (wo) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | rxdata (8 bit) (ro) | /
+ 0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
+
+- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
+
+ 0x00000800 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
+ | : | | = 0x00000800
+ | : | /
+ 0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
+ 0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
+
+
+===============================================================================
+ F L A S H M E M O R Y A L L O C A T I O N
+===============================================================================
+
+ 0x01800000 ---8-------------4|3-------------0-
+ | : | \
+ | : | |
+ | : | > 6 MByte ROM FS
+ | : | |
+ | : | /
+ 0x01200000 --+- - - - - - - -:- - - - - - - -+- - file system image(s)
+ | : | \
+ | : | |
+ | : | > 1728 kByte ucLinux
+ | : | |
+ | : | /
+ 0x01050000 --+- - - - - - - -:- - - - - - - -+- - os image(s)
+ | : | \
+ 0x01040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment
+ | : | |
+ | : | > 320 kByte U-Boot
+ | : | |
+ | : | |
+ | : | /
+ 0x01000000 --+- - - - - - - -:- - - - - - - -+- - u-boot _start()
+ 0x01000000 ---8-------------4|3-------------0-
+
+
+===============================================================================
+ R E F E R E N C E S
+===============================================================================
+[1] http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[2] http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[3] http://www.altera.com/literature/ds/ds_nios_pio.pdf
+[4] http://www.altera.com/literature/ds/ds_nios_spi.pdf
+[5] http://www.t13.org/index.html
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>
* We have only 16 Bit PCMCIA access on Socket 0
*/
+#ifdef CONFIG_ADNPESC1
+#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
+#else
#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
+#endif
#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
+#ifdef CONFIG_ADNPESC1
+#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
+#else
#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#endif
#define SMC_outb(d,r) ({ word __d = (byte)(d); \
word __w = SMC_inw((r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
#define RPC_LED_RX (0x07) /* LED = RX packet occurred */
#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
/* buggy schematic: LEDa -> yellow, LEDb --> green */
+#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
+ | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
+ | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
+#elif defined(CONFIG_ADNPESC1)
+/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
| (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
| (RPC_LED_100_10 << RPC_LSXB_SHFT) )
--- /dev/null
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************************************************
+ * Include the whole NIOS CPU configuration.
+ *
+ * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
+ *
+ ***********************************************************************/
+
+#if defined(CONFIG_NIOS_BASE_32)
+#include <configs/ADNPESC1_base_32.h>
+#else
+#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
+#endif
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU -- TOP-LEVEL
+ *----------------------------------------------------------------------*/
+#define CONFIG_NIOS 1 /* NIOS-32 core */
+#define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */
+#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
+#define CFG_HZ 1000 /* 1 msec time tick */
+#undef CFG_CLKS_IN_HZ
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
+ *----------------------------------------------------------------------*/
+#if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
+
+#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
+#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
+
+#else
+#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
+#endif
+
+#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
+
+#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
+#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
+
+#else
+
+#undef CFG_SRAM_BASE
+#undef CFG_SRAM_SIZE
+
+#endif
+
+#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION - For the most part, you can put things pretty
+ * much anywhere. This is pretty flexible for Nios. So here we make some
+ * arbitrary choices & assume that the monitor is placed at the end of
+ * a memory resource (so you must make sure TEXT_BASE is chosen
+ * appropriately -- this is very important if you plan to move your
+ * memory to another place as configured at this time !!!).
+ *
+ * -The heap is placed below the monitor.
+ * -Global data is placed below the heap.
+ * -The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
+#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
+
+#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
+#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
+#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
+#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size */
+
+#else
+#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT
+ *----------------------------------------------------------------------*/
+#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
+
+#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
+
+/* Mem addr of environment */
+#if defined(CONFIG_NIOS_BASE_32)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#else
+#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
+#endif
+
+#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
+#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
+
+#else
+#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
+#endif
+
+/*------------------------------------------------------------------------
+ * NIOS APPLICATION CODE BASE AREA
+ *----------------------------------------------------------------------*/
+#if ((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000)
+#define CFG_ADNPESC1_UPDATE_LOAD_ADDR "0x2000100"
+#define CFG_ADNPESC1_NIOS_APPL_ENTRY "0x1050000"
+#define CFG_ADNPESC1_NIOS_APPL_IDENT "0x105000c"
+#define CFG_ADNPESC1_NIOS_APPL_END "0x11fffff"
+#define CFG_ADNPESC1_FILESYSTEM_BASE "0x1200000"
+#define CFG_ADNPESC1_FILESYSTEM_END "0x17fffff"
+#else
+#error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h
+#endif
+#define CFG_ADNPESC1_NIOS_IDENTIFIER "Nios"
+
+/*------------------------------------------------------------------------
+ * BOOT ENVIRONMENT
+ *----------------------------------------------------------------------*/
+#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
+#define CFG_ADNPESC1_SLED_BOOT_OFF "sled boot off; "
+#define CFG_ADNPESC1_SLED_RED_BLINK "sled red blink; "
+#else
+#define CFG_ADNPESC1_SLED_BOOT_OFF
+#define CFG_ADNPESC1_SLED_RED_BLINK
+#endif
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTCOMMAND \
+ "if itest.s *$appl_ident_addr == \"$appl_ident_str\"; " \
+ "then " \
+ "wd off; " \
+ CFG_ADNPESC1_SLED_BOOT_OFF \
+ "go $appl_entry_addr; " \
+ "else " \
+ CFG_ADNPESC1_SLED_RED_BLINK \
+ "echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\
+ "echo *** invalid application at $appl_entry_addr; " \
+ "echo *** stop bootup...; " \
+ "fi"
+
+/*------------------------------------------------------------------------
+ * EXTRA ENVIRONMENT
+ *----------------------------------------------------------------------*/
+#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
+#define CFG_ADNPESC1_SLED_YELLO_ON "sled yellow on; "
+#define CFG_ADNPESC1_SLED_YELLO_OFF "sled yellow off; "
+#else
+#define CFG_ADNPESC1_SLED_YELLO_ON
+#define CFG_ADNPESC1_SLED_YELLO_OFF
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "update_allowed=0\0" \
+ "update_load_addr=" CFG_ADNPESC1_UPDATE_LOAD_ADDR "\0" \
+ "appl_entry_addr=" CFG_ADNPESC1_NIOS_APPL_ENTRY "\0" \
+ "appl_end_addr=" CFG_ADNPESC1_NIOS_APPL_END "\0" \
+ "appl_ident_addr=" CFG_ADNPESC1_NIOS_APPL_IDENT "\0" \
+ "appl_ident_str=" CFG_ADNPESC1_NIOS_IDENTIFIER "\0" \
+ "appl_name=ADNPESC1/base32/linux.bin\0" \
+ "appl_update=" \
+ "if itest.b $update_allowed != 0; " \
+ "then " \
+ CFG_ADNPESC1_SLED_YELLO_ON \
+ "tftp $update_load_addr $appl_name; " \
+ "protect off $appl_entry_addr $appl_end_addr; " \
+ "era $appl_entry_addr $appl_end_addr; " \
+ "cp.b $update_load_addr $appl_entry_addr $filesize; "\
+ CFG_ADNPESC1_SLED_YELLO_OFF \
+ "else " \
+ "echo *** update not allowed (update_allowed=$update_allowed); "\
+ "fi\0" \
+ "fs_base_addr=" CFG_ADNPESC1_FILESYSTEM_BASE "\0" \
+ "fs_end_addr=" CFG_ADNPESC1_FILESYSTEM_END "\0" \
+ "fs_name=ADNPESC1/base32/romfs.img\0" \
+ "fs_update=" \
+ "if itest.b $update_allowed != 0; " \
+ "then " \
+ CFG_ADNPESC1_SLED_YELLO_ON \
+ "tftp $update_load_addr $fs_name; " \
+ "protect off $fs_base_addr $fs_end_addr; " \
+ "era $fs_base_addr $fs_end_addr; " \
+ "cp.b $update_load_addr $fs_base_addr $filesize; "\
+ CFG_ADNPESC1_SLED_YELLO_OFF \
+ "else " \
+ "echo *** update not allowed (update_allowed=$update_allowed); "\
+ "fi\0" \
+ "uboot_name=ADNPESC1/base32/u-boot.bin\0" \
+ "uboot_loadnrun=" \
+ "if ping $serverip; " \
+ "then " \
+ CFG_ADNPESC1_SLED_YELLO_ON \
+ "tftp $update_load_addr $uboot_name; " \
+ "wd off; " \
+ "go $update_load_addr; " \
+ "else " \
+ "echo *** missing connection to $serverip; " \
+ "echo *** check your network and try again...; "\
+ "fi\0"
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if (CFG_NIOS_CPU_UART_NUMS != 0)
+
+#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
+
+#if (CFG_NIOS_CPU_UART0_BR != 0)
+#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
+#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
+#else
+#undef CFG_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE 115200
+#endif
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#else
+#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
+ * so an avalon bus timer is required.
+ *----------------------------------------------------------------------*/
+#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
+
+#if (CFG_NIOS_CPU_TICK_TIMER == 0)
+
+#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */
+#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ
+
+#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */
+
+#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
+#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
+#else
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
+
+#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */
+
+#if (CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
+#endif
+
+#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
+
+#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
+#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
+
+#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */
+
+#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
+#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
+#else
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
+
+#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */
+
+#if (CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
+#endif
+
+#endif /* CFG_NIOS_CPU_TICK_TIMER */
+
+#else
+#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * WATCHDOG (or better MAX823 supervisory circuite access)
+ *----------------------------------------------------------------------*/
+#define CONFIG_HW_WATCHDOG 1 /* board specific WD */
+
+#ifdef CONFIG_HW_WATCHDOG
+
+/* MAX823 supervisor -- watchdog enable port at: */
+#if (CFG_NIOS_CPU_WDENA_PIO == 0)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */
+#elif (CFG_NIOS_CPU_WDENA_PIO == 1)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */
+#elif (CFG_NIOS_CPU_WDENA_PIO == 2)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */
+#elif (CFG_NIOS_CPU_WDENA_PIO == 3)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */
+#elif (CFG_NIOS_CPU_WDENA_PIO == 4)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */
+#elif (CFG_NIOS_CPU_WDENA_PIO == 5)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */
+#elif (CFG_NIOS_CPU_WDENA_PIO == 6)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */
+#elif (CFG_NIOS_CPU_WDENA_PIO == 7)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */
+#elif (CFG_NIOS_CPU_WDENA_PIO == 8)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */
+#elif (CFG_NIOS_CPU_WDENA_PIO == 9)
+#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */
+#else
+#error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config
+#endif
+
+/* MAX823 supervisor -- watchdog trigger port at: */
+#if (CFG_NIOS_CPU_WDTOG_PIO == 0)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */
+#elif (CFG_NIOS_CPU_WDTOG_PIO == 1)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */
+#elif (CFG_NIOS_CPU_WDTOG_PIO == 2)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */
+#elif (CFG_NIOS_CPU_WDTOG_PIO == 3)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */
+#elif (CFG_NIOS_CPU_WDTOG_PIO == 4)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */
+#elif (CFG_NIOS_CPU_WDTOG_PIO == 5)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */
+#elif (CFG_NIOS_CPU_WDTOG_PIO == 6)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */
+#elif (CFG_NIOS_CPU_WDTOG_PIO == 7)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */
+#elif (CFG_NIOS_CPU_WDTOG_PIO == 8)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */
+#elif (CFG_NIOS_CPU_WDTOG_PIO == 9)
+#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */
+#else
+#error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config
+#endif
+
+#if defined(CONFIG_NIOS_BASE_32) /* NIOS CPU specifics */
+#define CONFIG_HW_WDENA_BIT 0 /* WD enable @ Bit 0 */
+#define CONFIG_HW_WDTOG_BIT 0 /* WD trigger @ Bit 0 */
+#define CONFIG_HW_WDPORT_WRONLY 1 /* each WD port wr/only*/
+#else
+#error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h
+#endif
+
+#endif /* CONFIG_HW_WATCHDOG */
+
+/*------------------------------------------------------------------------
+ * SERIAL PERIPHAREL INTERFACE
+ *----------------------------------------------------------------------*/
+#if (CFG_NIOS_CPU_SPI_NUMS == 1)
+
+#define CONFIG_NIOS_SPI 1 /* SPI support active */
+#define CFG_NIOS_SPIBASE CFG_NIOS_CPU_SPI0
+#define CFG_NIOS_SPIBITS CFG_NIOS_CPU_SPI0_BITS
+
+#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */
+#define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */
+
+#define __SPI_CMD_OFF 0 /* allow default commands: */
+ /* CFG_CMD_SPI */
+ /* CFG_CMD_DATE */
+
+#else
+#undef CONFIG_NIOS_SPI /* NO SPI support */
+#define __SPI_CMD_OFF ( CFG_CMD_SPI \
+ | CFG_CMD_DATE \
+ )
+#endif
+
+/*------------------------------------------------------------------------
+ * Ethernet -- needs work!
+ *----------------------------------------------------------------------*/
+#if (CFG_NIOS_CPU_LAN_NUMS == 1)
+
+#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
+
+#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
+#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
+#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+
+#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
+#define CONFIG_SMC_USE_32_BIT 1
+#else /* no */
+#undef CONFIG_SMC_USE_32_BIT
+#endif
+
+#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
+
+ /********************************************/
+ /* !!! CS8900 is __not__ tested on NIOS !!! */
+ /********************************************/
+#define CONFIG_DRIVER_CS8900 /* Using CS8900 */
+#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+
+#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
+#undef CS8900_BUS16
+#define CS8900_BUS32 1
+#else /* no */
+#define CS8900_BUS16 1
+#undef CS8900_BUS32
+#endif
+
+#else
+#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
+#endif
+
+#define CONFIG_ETHADDR 02:80:ae:20:60:6f
+#define CONFIG_NETMASK 255.255.255.248
+#define CONFIG_IPADDR 192.168.161.84
+#define CONFIG_SERVERIP 192.168.161.85
+
+#else
+#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
+#endif
+
+/*------------------------------------------------------------------------
+ * STATUS LEDs
+ *----------------------------------------------------------------------*/
+#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
+
+#if (CFG_NIOS_CPU_LED_PIO == 0)
+
+#define STATUS_LED_BASE CFG_NIOS_CPU_PIO0
+#define STATUS_LED_BITS CFG_NIOS_CPU_PIO0_BITS
+#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
+
+#if (CFG_NIOS_CPU_PIO0_TYPE == 1)
+#define STATUS_LED_WRONLY 1
+#else
+#undef STATUS_LED_WRONLY
+#endif
+
+#elif (CFG_NIOS_CPU_LED_PIO == 1)
+
+#define STATUS_LED_BASE CFG_NIOS_CPU_PIO1
+#define STATUS_LED_BITS CFG_NIOS_CPU_PIO1_BITS
+#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
+
+#if (CFG_NIOS_CPU_PIO1_TYPE == 1)
+#define STATUS_LED_WRONLY 1
+#else
+#undef STATUS_LED_WRONLY
+#endif
+
+#elif (CFG_NIOS_CPU_LED_PIO == 2)
+
+#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
+#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
+#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
+
+#if (CFG_NIOS_CPU_PIO2_TYPE == 1)
+#define STATUS_LED_WRONLY 1
+#else
+#undef STATUS_LED_WRONLY
+#endif
+
+#elif (CFG_NIOS_CPU_LED_PIO == 3)
+
+#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
+
+#elif (CFG_NIOS_CPU_LED_PIO == 4)
+
+#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
+
+#elif (CFG_NIOS_CPU_LED_PIO == 5)
+
+#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
+
+#elif (CFG_NIOS_CPU_LED_PIO == 6)
+
+#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
+
+#elif (CFG_NIOS_CPU_LED_PIO == 7)
+
+#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
+
+#elif (CFG_NIOS_CPU_LED_PIO == 8)
+
+#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
+
+#elif (CFG_NIOS_CPU_LED_PIO == 9)
+
+#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
+
+#else
+#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
+#endif
+
+#define CONFIG_STATUS_LED 1 /* enable status led driver */
+
+#define STATUS_LED_BIT (1 << 0) /* LED[0] */
+#define STATUS_LED_STATE STATUS_LED_BLINKING
+#define STATUS_LED_BOOT_STATE STATUS_LED_OFF
+#define STATUS_LED_PERIOD (CFG_HZ / 2) /* ca. 1 Hz */
+#define STATUS_LED_BOOT 0 /* boot LED */
+
+#if (STATUS_LED_BITS > 1)
+#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_PERIOD1 (CFG_HZ / 10) /* ca. 5 Hz */
+#define STATUS_LED_RED 1 /* fail LED */
+#endif
+
+#if (STATUS_LED_BITS > 2)
+#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
+#define STATUS_LED_STATE2 STATUS_LED_OFF
+#define STATUS_LED_PERIOD2 (CFG_HZ / 2) /* ca. 1 Hz */
+#define STATUS_LED_YELLOW 2 /* info LED */
+#endif
+
+#if (STATUS_LED_BITS > 3)
+#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
+#define STATUS_LED_STATE3 STATUS_LED_OFF
+#define STATUS_LED_PERIOD3 (CFG_HZ / 2) /* ca. 1 Hz */
+#define STATUS_LED_GREEN 3 /* info LED */
+#endif
+
+#define STATUS_LED_PAR 1 /* makes status_led.h happy */
+
+#endif /* CFG_NIOS_CPU_PIO_NUMS */
+
+/*------------------------------------------------------------------------
+ * Diagnostics / Power On Self Tests
+ *----------------------------------------------------------------------*/
+#define CONFIG_POST CFG_POST_RTC
+#define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_BMP | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_DOC | \
+ CFG_CMD_DTT | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ CFG_CMD_FAT | \
+ CFG_CMD_FDC | \
+ CFG_CMD_FDOS | \
+ CFG_CMD_HWFLOW | \
+ CFG_CMD_IDE | \
+ CFG_CMD_I2C | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_KGDB | \
+ CFG_CMD_NAND | \
+ CFG_CMD_NFS | \
+ CFG_CMD_MMC | \
+ CFG_CMD_MII | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PCMCIA | \
+ CFG_CMD_SCSI | \
+ CFG_CMD_VFD | \
+ CFG_CMD_USB | \
+ __SPI_CMD_OFF ) )
+
+
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * KGDB
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 9600
+#endif
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser
+ undef to save memory */
+#define CFG_PROMPT "ADNPESC1 > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 64 /* max number of command args*/
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "[]> "
+#endif
+
+/* Default load address */
+#if (CFG_SRAM_SIZE != 0)
+
+/* default in SRAM */
+#define CFG_LOAD_ADDR CFG_SRAM_BASE
+
+#elif (CFG_SDRAM_SIZE != 0)
+
+/* default in SDRAM */
+#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
+#if 1
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
+#else
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x400000)
+#endif
+#else
+#define CFG_LOAD_ADDR CFG_SDRAM_BASE
+#endif
+
+#else
+#undef CFG_LOAD_ADDR /* force error break */
+#endif
+
+
+/* MEM test area */
+#if (CFG_SDRAM_SIZE != 0)
+
+/* SDRAM begin to stack area (1MB stack) */
+#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
+#if 0
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
+#else
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x400000)
+#endif
+#else
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#endif
+
+#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
+#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
+
+#else
+#undef CFG_MEMTEST_START /* force error break */
+#undef CFG_MEMTEST_END
+#endif
+
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ADNPESC1_BASE_32_H
+#define __CONFIG_ADNPESC1_BASE_32_H
+
+/*
+ * NIOS CPU configuration. (PART OF configs/ADNPESC1.h)
+ *
+ * Here we must define CPU dependencies. Any unsupported option have to
+ * be undefined or defined with zero, example CPU without data cache / OCI:
+ *
+ * #define CFG_NIOS_CPU_ICACHE 4096
+ * #define CFG_NIOS_CPU_DCACHE 0
+ * #undef CFG_NIOS_CPU_OCI_BASE
+ * #undef CFG_NIOS_CPU_OCI_SIZE
+ */
+
+/* CPU core */
+#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */
+#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */
+#define CFG_NIOS_CPU_DCACHE (0) /* data cache */
+#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */
+#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_STACK 0x03000000 /* stack top addr */
+#define CFG_NIOS_CPU_VEC_BASE 0x02000000 /* IRQ vectors addr */
+#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */
+#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */
+#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */
+#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */
+ /* yes(1) */
+
+/* The offset address in flash to check for the Nios signature "Ni".
+ * (see GM_FlashExec in germs_monitor.s) */
+#define CFG_NIOS_CPU_EXES_OFFS 0x0C
+
+/* on-chip extensions */
+#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */
+#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */
+
+#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */
+#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */
+
+#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */
+#undef CFG_NIOS_CPU_OCI_SIZE /* size */
+
+/* timer */
+#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */
+
+#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */
+#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */
+#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */
+#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */
+ /* yes(1) */
+
+/* serial i/o */
+#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */
+
+#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */
+#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */
+#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */
+#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */
+#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */
+#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */
+ /* odd(1) */
+ /* even(2) */
+#define CFG_NIOS_CPU_UART0_HS 1 /* handshake: no(0) */
+ /* crts(1) */
+#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */
+ /* yes(1) */
+
+#define CFG_NIOS_CPU_UART1 0x00000820 /* UART1 addr */
+#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */
+#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */
+#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */
+#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */
+#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */
+ /* odd(1) */
+ /* even(2) */
+#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */
+ /* crts(1) */
+#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */
+ /* yes(1) */
+
+/* serial peripheral i/o */
+#define CFG_NIOS_CPU_SPI_NUMS 1 /* number of spis */
+
+#define CFG_NIOS_CPU_SPI0 0x000008c0 /* SPI0 addr */
+#define CFG_NIOS_CPU_SPI0_IRQ 25 /* IRQ */
+#define CFG_NIOS_CPU_SPI0_BITS 16 /* data bit */
+#define CFG_NIOS_CPU_SPI0_MA 1 /* is master: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_SPI0_SLN 1 /* num slaves */
+#define CFG_NIOS_CPU_SPI0_TCLK 250000 /* clock (Hz) */
+#define CFG_NIOS_CPU_SPI0_TDELAY 2 /* delay (usec) */
+#define CFG_NIOS_CPU_SPI0_FB 0 /* first bit msb(0) */
+ /* lsb(1) */
+
+/* parallel i/o */
+#define CFG_NIOS_CPU_PIO_NUMS 14 /* number of parports */
+
+#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */
+#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */
+#define CFG_NIOS_CPU_PIO0_BITS 8 /* number of bits */
+#define CFG_NIOS_CPU_PIO0_TYPE 0 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */
+#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */
+#define CFG_NIOS_CPU_PIO1_BITS 8 /* number of bits */
+#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO2 0x00000880 /* PIO2 addr */
+#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */
+#define CFG_NIOS_CPU_PIO2_BITS 4 /* number of bits */
+#define CFG_NIOS_CPU_PIO2_TYPE 0 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */
+#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
+#define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */
+#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
+#define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO4 0x000008a0 /* PIO4 addr */
+#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */
+#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO4_TYPE 1 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO5 0x000008b0 /* PIO5 addr */
+#undef CFG_NIOS_CPU_PIO5_IRQ /* w/o IRQ */
+#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO5_TYPE 1 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO5_CAP 0 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO5_EDGE 0 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO5_ITYPE 0 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO6 0x00000900 /* PIO6 addr */
+#define CFG_NIOS_CPU_PIO6_IRQ 20 /* IRQ */
+#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO6_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO6_CAP 1 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO6_EDGE 2 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO6_ITYPE 1 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO7 0x00000910 /* PIO7 addr */
+#define CFG_NIOS_CPU_PIO7_IRQ 31 /* IRQ */
+#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO7_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO7_CAP 1 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO7_EDGE 2 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO7_ITYPE 1 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO8 0x00000920 /* PIO8 addr */
+#define CFG_NIOS_CPU_PIO8_IRQ 32 /* IRQ */
+#define CFG_NIOS_CPU_PIO8_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO8_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO8_CAP 1 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO8_EDGE 2 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO8_ITYPE 1 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO9 0x00000930 /* PIO9 addr */
+#define CFG_NIOS_CPU_PIO9_IRQ 33 /* IRQ */
+#define CFG_NIOS_CPU_PIO9_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO9_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO9_CAP 1 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO9_EDGE 2 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO9_ITYPE 1 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO10 0x00000940 /* PIO10 addr */
+#define CFG_NIOS_CPU_PIO10_IRQ 34 /* IRQ */
+#define CFG_NIOS_CPU_PIO10_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO10_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO10_CAP 1 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO10_EDGE 2 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO10_ITYPE 1 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO11 0x00000950 /* PIO11 addr */
+#define CFG_NIOS_CPU_PIO11_IRQ 35 /* IRQ */
+#define CFG_NIOS_CPU_PIO11_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO11_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO11_CAP 1 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO11_EDGE 2 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO11_ITYPE 1 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO12 0x00000960 /* PIO12 addr */
+#define CFG_NIOS_CPU_PIO12_IRQ 36 /* IRQ */
+#define CFG_NIOS_CPU_PIO12_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO12_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO12_CAP 1 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO12_EDGE 2 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO12_ITYPE 1 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+#define CFG_NIOS_CPU_PIO13 0x00000970 /* PIO113 addr */
+#define CFG_NIOS_CPU_PIO13_IRQ 37 /* IRQ */
+#define CFG_NIOS_CPU_PIO13_BITS 1 /* number of bits */
+#define CFG_NIOS_CPU_PIO13_TYPE 2 /* io type: tris(0) */
+ /* out(1) */
+ /* in(2) */
+#define CFG_NIOS_CPU_PIO13_CAP 1 /* capture: no(0) */
+ /* yes(1) */
+#define CFG_NIOS_CPU_PIO13_EDGE 2 /* edge type: none(0) */
+ /* fall(1) */
+ /* rise(2) */
+ /* any(3) */
+#define CFG_NIOS_CPU_PIO13_ITYPE 1 /* IRQ type: none(0) */
+ /* level(1)*/
+ /* edge(2) */
+
+/* IDE i/f */
+#define CFG_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */
+
+#define CFG_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */
+#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */
+
+#define CFG_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */
+#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */
+
+/* memory accessibility */
+#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */
+#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */
+
+#define CFG_NIOS_CPU_SDRAM_BASE 0x02000000 /* board SDRAM addr */
+#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */
+
+#define CFG_NIOS_CPU_FLASH_BASE 0x01000000 /* board Flash addr */
+#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */
+
+/* LAN */
+#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */
+
+#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */
+#define CFG_NIOS_CPU_LAN0_OFFS (0) /* offset */
+#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */
+#define CFG_NIOS_CPU_LAN0_BUSW 16 /* buswidth*/
+#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */
+ /* cs8900(1) */
+ /* ex: openmac(2) */
+ /* ex: alteramac(3) */
+
+/* external extension */
+#define CFG_NIOS_CPU_CS0_BASE 0x40000000 /* board EXT0 addr */
+#define CFG_NIOS_CPU_CS0_SIZE (16*1024*1024) /* max. 16 MB size */
+
+#define CFG_NIOS_CPU_CS1_BASE 0x41000000 /* board EXT1 addr */
+#define CFG_NIOS_CPU_CS1_SIZE (16*1024*1024) /* max. 16 MB size */
+
+#define CFG_NIOS_CPU_CS2_BASE 0x42000000 /* board EXT2 addr */
+#define CFG_NIOS_CPU_CS2_SIZE (16*1024*1024) /* max. 16 MB size */
+
+#define CFG_NIOS_CPU_CS3_BASE 0x43000000 /* board EXT3 addr */
+#define CFG_NIOS_CPU_CS3_SIZE (16*1024*1024) /* max. 16 MB size */
+
+/* symbolic redefinition (undef, if not present) */
+#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/
+#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */
+
+#define CFG_NIOS_CPU_PORTA_PIO 0 /* PIO0: Port A */
+#define CFG_NIOS_CPU_PORTB_PIO 1 /* PIO1: Port D */
+#define CFG_NIOS_CPU_PORTC_PIO 2 /* PIO2: Port C */
+#define CFG_NIOS_CPU_RCM_PIO 3 /* PIO3: RCM jumper */
+#define CFG_NIOS_CPU_WDENA_PIO 4 /* PIO4: watchdog enable*/
+#define CFG_NIOS_CPU_WDTOG_PIO 5 /* PIO5: watchdog trigg.*/
+
+/* PIOx: LED bar */
+#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
+#define CFG_NIOS_CPU_LED_PIO CFG_NIOS_CPU_PORTA_PIO
+#else
+#undef CFG_NIOS_CPU_LED_PIO /* no LED bar */
+#endif
+
+#endif /* __CONFIG_ADNPESC1_BASE_32_H */
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