stm32mp: update the mmu configuration for SPL and prereloc

Overidde the weak function dram_bank_mmu_setup() to set the DDR
(preloc case) or the SYSRAM (in SPL case) executable before to enable
the MMU and configure DACR.

This weak function is called in dcache_enable/mmu_setup.

This patchs avoids a permission access issue when the DDR is marked
executable (by calling mmu_set_region_dcache_behaviour with
DCACHE_DEFAULT_OPTION) after MMU setup and domain access permission
activation with DACR in dcache_enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 3faa4ec18a4ff1bf0e659e85f9af25b2ab2bae61..d332f5aecd00920ac400a4d2ec1137d604e25f2f 100644 (file)
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -211,6 +211,35 @@ u32 get_bootmode(void)
                    TAMP_BOOT_MODE_SHIFT;
 }
 
+/*
+ * weak function overidde: set the DDR/SYSRAM executable before to enable the
+ * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
+ */
+void dram_bank_mmu_setup(int bank)
+{
+       struct bd_info *bd = gd->bd;
+       int     i;
+       phys_addr_t start;
+       phys_size_t size;
+
+       if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+               start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
+               size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
+       } else if (gd->flags & GD_FLG_RELOC) {
+               /* bd->bi_dram is available only after relocation */
+               start = bd->bi_dram[bank].start;
+               size =  bd->bi_dram[bank].size;
+       } else {
+               /* mark cacheable and executable the beggining of the DDR */
+               start = STM32_DDR_BASE;
+               size = CONFIG_DDR_CACHEABLE_SIZE;
+       }
+
+       for (i = start >> MMU_SECTION_SHIFT;
+            i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
+            i++)
+               set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
 /*
  * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
  * MMU/TLB is updated in enable_caches() for U-Boot after relocation
@@ -226,17 +255,8 @@ static void early_enable_caches(void)
        gd->arch.tlb_size = PGTABLE_SIZE;
        gd->arch.tlb_addr = (unsigned long)&early_tlb;
 
+       /* enable MMU (default configuration) */
        dcache_enable();
-
-       if (IS_ENABLED(CONFIG_SPL_BUILD))
-               mmu_set_region_dcache_behaviour(
-                       ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
-                       ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
-                       DCACHE_DEFAULT_OPTION);
-       else
-               mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
-                                               CONFIG_DDR_CACHEABLE_SIZE,
-                                               DCACHE_DEFAULT_OPTION);
 }
 
 /*