the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address.
-- CONFIG_SYS_SDRAM_BASE:
+- CFG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
- CONFIG_SYS_FLASH_BASE:
static void arc_ioc_setup(void)
{
/* IOC Aperture start is equal to DDR start */
- unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+ unsigned int ap_base = CFG_SYS_SDRAM_BASE;
/* IOC Aperture size is equal to DDR size */
- long ap_size = CONFIG_SYS_SDRAM_SIZE;
+ long ap_size = CFG_SYS_SDRAM_SIZE;
/* Unsupported configuration. See [ NOTE 2 ] for more details. */
if (!slc_exists())
timer_init();
gd->cpu_clk = get_board_sys_clk();
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
cache_init();
*/
static void __secure ls1_save_ddr_head(void)
{
- const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+ const char *src = (const char *)CFG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
}
#endif
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
mmu_change_region_attr(
- CONFIG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_BASE,
gd->ram_size,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_TYPE_VALID);
} else {
mmu_change_region_attr(
- CONFIG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_BASE,
CONFIG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
arch = "arm";
os = "tee";
compression = "none";
- load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
- entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
+ load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+ entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
blob-ext {
filename = "tee.bin";
(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
(DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
- (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
+ (CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
#define CONFIG_IPROC
/* Memory Info */
-#define CONFIG_SYS_SDRAM_BASE 0x61000000
+#define CFG_SYS_SDRAM_BASE 0x61000000
#endif /* __IPROC_COMMON_CONFIGS_H */
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int i = 0, rc;
struct udevice *dev;
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
while (1) {
rc = uclass_get_device(UCLASS_MISC, i++, &dev);
.word CONFIG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM1
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM1
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
SMRDATA1E:
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
.word CONFIG_SYS_SDRC_MDR_VAL
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL1
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL1
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL6
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL7
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL8
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL9
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL2
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL3
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL4
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL5
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL6
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL7
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL8
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL9
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL10
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL10
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL11
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL11
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL12
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL12
/* User reset enable*/
.word AT91_ASM_RSTC_MR
.word CONFIG_SYS_RSTC_RMR_VAL
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
* better have similar timings, since there's only a single adjustment that is
* shared by both chips).
*/
-const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
+const unsigned int test_addr = CFG_SYS_SDRAM_BASE;
/* Test pattern with which RAM will be tested */
static const unsigned int test_pattern[] = {
int i;
for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
- if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+ if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
int i;
for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
- if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+ if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
* Get actual RAM size, so we can adjust DDR row size for <512M
* memories
*/
- ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
+ ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M);
if (ram_size < SZ_512M) {
mem_ddr.rowaddr = 14;
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
int board_init(void)
{
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FEC_MXC
setup_fec();
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = imx_ddr_size();
return 0;
void spl_enable_dcache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+ phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
dram_init();
O_I_WB_RD_WR_ALLOC, REGION_8MB},
/* U-Boot's code area marking it as WB and Write allocate */
- {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
+ {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_2GB},
/* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
{0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,
}
ddr3_ecc_init_range(base);
- ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
+ ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size);
/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
{
u32 i;
- if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+ if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) &&
((size_t)preloader_param % sizeof(size_t) == 0) &&
preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
preloader_param->dram_rank_num <=
for (i = 0; i < preloader_param->dram_rank_num; i++)
gd->ram_size += preloader_param->dram_rank_size[i];
} else {
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
SZ_2G);
}
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0;
}
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0;
}
static struct mm_region ac5_mem_map[] = {
{
/* RAM */
- .phys = CONFIG_SYS_SDRAM_BASE,
- .virt = CONFIG_SYS_SDRAM_BASE,
+ .phys = CFG_SYS_SDRAM_BASE,
+ .virt = CFG_SYS_SDRAM_BASE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
},
/*
* Config single DRAM bank
*/
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
- unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
+ unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
return (gd->ram_top > top) ? top : gd->ram_top;
}
*/
phys_size_t max_bank0_size = SZ_4G - SZ_1G;
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size <= max_bank0_size) {
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
sdram_init();
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
}
#endif
/* Set region1 memory with 0 */
rgn_start = (regs->emif_ecc_address_range_1 &
EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
- rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+ rgn = rgn_start + CFG_SYS_SDRAM_BASE;
size = (regs->emif_ecc_address_range_1 &
EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
/* Set region2 memory with 0 */
rgn_start = (regs->emif_ecc_address_range_2 &
EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
- rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+ rgn = rgn_start + CFG_SYS_SDRAM_BASE;
size = (regs->emif_ecc_address_range_2 &
EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
mapped_size = 0;
section_cnt = 3;
- sys_addr = CONFIG_SYS_SDRAM_BASE;
+ sys_addr = CFG_SYS_SDRAM_BASE;
emif1_size = get_emif_mem_size(EMIF1_BASE);
emif2_size = get_emif_mem_size(EMIF2_BASE);
debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
size_prog = log_2_n_round_down(size_prog);
size_prog = (1 << size_prog);
- size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
size_prog);
/* Compare with the size programmed */
if (size_detect != size_prog) {
*/
if (sec_mem_start == 0)
sec_mem_start =
- (CONFIG_SYS_SDRAM_BASE + (
+ (CFG_SYS_SDRAM_BASE + (
#if defined(CONFIG_OMAP54XX)
omap_sdram_size()
#else
- get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE)
#endif
- sec_mem_size));
/* This is called after dram_init() so use get_ram_size result */
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
int dram_init_banksize(void)
{
- size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+ size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE),
(unsigned long)(gd->ram_top));
#ifdef CONFIG_ARM64
#ifdef CONFIG_SPL_OPTEE_IMAGE
struct tos_parameter_t *tos_parameter;
- tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+ tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE +
TRUST_PARAMETER_OFFSET);
if (tos_parameter->tee_mem.flags == 1) {
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
- - CONFIG_SYS_SDRAM_BASE;
+ - CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
tos_parameter->tee_mem.size;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
} else {
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
/* Reserve 32M for OPTEE with TA */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x2000000;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
}
#else
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
#endif
#endif
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
- unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
+ unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
return (gd->ram_top > top) ? top : gd->ram_top;
}
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
- writel(0, CONFIG_SYS_SDRAM_BASE);
- writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+ writel(0, CFG_SYS_SDRAM_BASE);
+ writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
dsb();
/* Check if the same value is actually observed when reading back */
- return readl(CONFIG_SYS_SDRAM_BASE) ==
- readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
+ return readl(CFG_SYS_SDRAM_BASE) ==
+ readl((ulong)CFG_SYS_SDRAM_BASE + offset);
}
#endif
u32 k = 0;
for (k = 0; k < 32; k++)
- writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k);
+ writel(k, CFG_SYS_SDRAM_BASE + 4 * k);
for (k = 0; k < 32; k++) {
- if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k)
+ if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k)
return 0;
}
return 1;
dram_para_setup(para);
dram_scan_readpipe(para);
for (i = 0; i < 32; i++) {
- *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
- *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
+ *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
+ *((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
}
for (i = 0; i < 32; i++) {
- val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i));
+ val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i));
if (val1 == 0x22)
count++;
}
para->row_width = rowflag;
dram_para_setup(para);
if (colflag == 10) {
- addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000;
- addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000;
+ addr1 = CFG_SYS_SDRAM_BASE + 0x400000;
+ addr2 = CFG_SYS_SDRAM_BASE + 0xc00000;
} else {
- addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000;
- addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000;
+ addr1 = CFG_SYS_SDRAM_BASE + 0x200000;
+ addr2 = CFG_SYS_SDRAM_BASE + 0x600000;
}
for (i = 0; i < 32; i++) {
*((u8 *)(addr1 + i)) = 0x33;
static void simple_dram_check(void)
{
- volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE;
+ volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE;
int i;
for (i = 0; i < 0x40; i++)
*/
static void mctl_r40_detect_rank_count(struct dram_para *para)
{
- ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE +
+ ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE +
mctl_calc_rank_size(¶->ranks[0]);
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
{
- mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]);
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, ¶->ranks[0]);
if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) {
- mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]);
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]);
}
}
/* fall back to default DRAM bank size computation */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
#ifdef CONFIG_PCI
/* fall back to default usable RAM computation */
- return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
+ return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
}
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
-#if (CONFIG_SYS_SDRAM_BASE == 0)
+#if (CFG_SYS_SDRAM_BASE == 0)
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
* software workaround for SDRAM opeartion after exiting LIMP
* mode errata
*/
- out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
+ out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE);
#endif
/* wait for DQS logic to relock */
#ifdef CONFIG_PCI
#define CFG_SYS_PCI_BAR0 (0x40000000)
-#define CFG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
-#define CFG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M547x */
int arch_initr_trap(void)
{
- trap_init(CONFIG_SYS_SDRAM_BASE);
+ trap_init(CFG_SYS_SDRAM_BASE);
return 0;
}
int arch_initr_trap(void)
{
- trap_init(CONFIG_SYS_SDRAM_BASE);
+ trap_init(CFG_SYS_SDRAM_BASE);
return 0;
}
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
- return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
+ return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
}
int print_cpuinfo(void)
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
+#if CFG_SYS_SDRAM_SIZE <= SZ_64M
#define MSCC_RAM_TLB_SIZE SZ_64M
#define MSCC_ATTRIB2 MMU_REGIO_INVAL
-#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
+#elif CFG_SYS_SDRAM_SIZE <= SZ_128M
#define MSCC_RAM_TLB_SIZE SZ_64M
#define MSCC_ATTRIB2 MMU_REGIO_RW
-#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
+#elif CFG_SYS_SDRAM_SIZE <= SZ_256M
#define MSCC_RAM_TLB_SIZE SZ_256M
#define MSCC_ATTRIB2 MMU_REGIO_INVAL
-#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
+#elif CFG_SYS_SDRAM_SIZE <= SZ_512M
#define MSCC_RAM_TLB_SIZE SZ_256M
#define MSCC_ATTRIB2 MMU_REGIO_RW
#else
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
#include <mach/common.h>
#define MIPS_VCOREIII_MEMORY_DDR3
-#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE
+#define MIPS_VCOREIII_DDR_SIZE CFG_SYS_SDRAM_SIZE
#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */
#include "dram.h"
#ifndef CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_SP_OFFSET)
#endif
{
if (IS_ENABLED(CONFIG_RAM_OCTEON)) {
/* Map a maximum of 256MiB - return not size but address */
- return CONFIG_SYS_SDRAM_BASE + min(gd->ram_size,
+ return CFG_SYS_SDRAM_BASE + min(gd->ram_size,
UBOOT_RAM_SIZE_MAX);
} else {
return gd->ram_top;
if (ret)
return ret;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#ifndef CONFIG_ROM_STUBS
copy_exception_trampoline();
#endif
/*
* Set up LAWBAR for all of DDR.
*/
- ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+ ecm->bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
debug("DDR:bar=0x%08x\n", ecm->bar);
debug("DDR:ar=0x%08x\n", ecm->ar);
defined(CONFIG_ARCH_QEMU_E500)
gd->ram_size = fsl_ddr_sdram_size();
#else
- gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
return 0;
/* use last 4K of mapped memory */
bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
- CONFIG_SYS_SDRAM_BASE - 4096;
+ CFG_SYS_SDRAM_BASE - 4096;
if (pagesize)
*pagesize = 4096;
int j;
tbl->start_addr[i] =
- (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE);
+ (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE);
tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED));
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
#ifdef DEBUG
if (((u64)bootmap_base + bootm_size) >
- (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size))
+ (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size))
puts("WARNING: bootm_low + bootm_size exceed total memory\n");
if ((bootmap_base + bootm_size) > get_effective_memsize())
puts("WARNING: bootm_low + bootm_size exceed eff. memory\n");
{
state = &main_state;
- state->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ state->ram_size = CFG_SYS_SDRAM_SIZE;
state->ram_buf = os_malloc(state->ram_size);
if (!state->ram_buf) {
printf("Out of memory\n");
};
memory {
- reg = <0 CONFIG_SYS_SDRAM_SIZE>;
+ reg = <0 CFG_SYS_SDRAM_SIZE>;
};
reserved-memory {
};
memory {
- reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>;
+ reg = /bits/ 64 <0 CFG_SYS_SDRAM_SIZE>;
};
reserved-memory {
MEMORY
{
- ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE
+ ram : ORIGIN = CFG_SYS_SDRAM_BASE, LENGTH = CFG_SYS_SDRAM_SIZE
}
ENTRY(_start)
int dram_init(void)
{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200);
set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001);
set_sh_linux_param((unsigned long)param + INITRD_START,
- GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE));
+ GET_INITRD_START(images->rd_start, CFG_SYS_SDRAM_BASE));
set_sh_linux_param((unsigned long)param + INITRD_SIZE,
images->rd_end - images->rd_start);
}
int arch_cpu_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
asm (" nop");
-#ifdef CONFIG_SYS_SDRAM_BASE0
- MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)|
+#ifdef CFG_SYS_SDRAM_BASE0
+ MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)|
MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
MCFSDRAMC_DACR_PS_32;
asm (" nop");
for (i = 0; i < 10; i++)
asm (" nop");
- *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
+ *(unsigned long *)(CFG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
asm (" nop");
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
asm (" nop");
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
asm (" nop");
/* write SDRAM mode register */
- *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
+ *(unsigned long *)(CFG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
asm (" nop");
- size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024;
+ size += CFG_SYS_SDRAM_SIZE0 * 1024 * 1024;
#endif
-#ifdef CONFIG_SYS_SDRAM_BASE1xx
- MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
+#ifdef CFG_SYS_SDRAM_BASE1xx
+ MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SYS_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
- *(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
+ *(unsigned short *) (CFG_SYS_SDRAM_BASE1) = 0xA5A5;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
- *(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
- size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
+ *(unsigned int *) (CFG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
+ size += CFG_SYS_SDRAM_SIZE1 * 1024 * 1024;
#endif
gd->ram_size = size;
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init(void)
{
gd->ram_size = smc_dram_size(0);
- gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size -= CFG_SYS_SDRAM_BASE;
mem_map_fill();
return 0;
int dram_init(void)
{
gd->ram_size = smc_dram_size(0);
- gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size -= CFG_SYS_SDRAM_BASE;
mem_map_fill();
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init (void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
*
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
- gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
REMAPPED_FLASH_SZ,
0x01000000 << sdram_shift);
}
#else
- gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
REMAPPED_FLASH_SZ,
PHYS_SDRAM_1_SIZE);
#endif /* CM_SPD_DETECT */
int dram_init(void)
{
gd->ram_size =
- get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
+ get_ram_size((long *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
return 0;
}
* GPIO configuration for bus should be set correctly from reset,
* so we do not care! First, set up address space: at this point,
* we should be running from internal SRAM;
- * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
+ * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM,
* and do not care where it is
*/
- __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
+ __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
&sdp->cs0);
- __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
+ __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
&sdp->cs1);
/*
* I am not sure from the data sheet, but it seems burst length
*/
__raw_writel(0x71462C00, &sdp->ctrl);
/* Dummy write to start SDRAM */
- writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0, CFG_SYS_SDRAM_BASE);
#endif
/*
* (Do not rely on the SDCS register(s) being set to 0x00000000
* during reset as stated in the data sheet.)
*/
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- 0x80000000 - CONFIG_SYS_SDRAM_BASE);
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+ 0x80000000 - CFG_SYS_SDRAM_BASE);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9260ek_nand_hw_init();
int dram_init(void)
{
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ (void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
#endif
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9261ek_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
/* arch number of AT91SAM9263EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9263ek_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9m10g45ek_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
at91sam9n12ek_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
/* arch number of AT91SAM9RLEK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9rlek_nand_hw_init();
int dram_init(void)
{
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ (void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9x5ek_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
sam9x60ek_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d3_xplained_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d3xek_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d4_xplained_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d4ek_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
board_leds_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
ret = gurnard_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_MTD_RAW_NAND
gpmc_init();
if (read_eeprom() < 0)
puts("EEPROM Content Invalid.\n");
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
* Address of boot parameters passed to kernel
* Use default offset 0x100
*/
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
*/
int dram_init(void)
{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
usb_a9263_nand_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
/* Dummy write to start SDRAM */
*((volatile unsigned long *) 0) = 0;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
set_i2c_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
unsigned long ram_size;
config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
- ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000);
if (ram_size == 0x80000000 ||
ram_size == 0x40000000 ||
ram_size == 0x20000000)
ddr3_emif_regs.sdram_config = 0x638453B2;
config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
- ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000);
if (ram_size == 0x08000000)
return;
out_be32(&memctl->memc_mcr, 0x80002038);
udelay(200);
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
SDRAM_MAX_SIZE);
return 0;
int
board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x2000;
return 0;
}
int
dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_64M);
return 0;
}
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ (void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Set adress of boot parameters. */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Initialize UARTs and power management. */
ethernut5_power_init();
#ifdef CONFIG_CMD_NAND
{
*err = 0;
/* QEMU loads a generated DTB for us at the start of RAM. */
- return (void *)CONFIG_SYS_SDRAM_BASE;
+ return (void *)CFG_SYS_SDRAM_BASE;
}
void enable_caches(void)
meesc_ethercat_hw_init();
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
meesc_nand_hw_init();
/* get the address of ddr date from SPARECR3 */
src = (u64 *)in_le32(&scfg->sparecr[2]);
- dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+ dst = (u64 *)CFG_SYS_SDRAM_BASE;
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst++ = *src++;
/* get the address of ddr date from SPARECR3 */
src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
- dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
+ dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst-- = *src--;
else
gd->ram_size = SYS_SDRAM_SIZE_512;
#else
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#endif
}
return 0;
gd->ram_size = SYS_SDRAM_SIZE_512;
}
#else
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#endif
mmdc_init(&mparam);
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
};
mmdc_init(&mparam);
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
mmdc_init(&mparam);
#endif
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
- out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
- out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CONFIG_SYS_SDRAM_BASE1
- out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+#ifdef CFG_SYS_SDRAM_BASE1
+ out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
#endif
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
asm("nop");
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
asm("nop");
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
asm("nop");
udelay(100);
GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
GPIO_PAR_SDRAM_SDCS(3));
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
/* Initialize DACR0 */
out_be32(&sdram->dacr0,
- SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+ SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) |
SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
SDRAMC_DARCn_PS_32);
asm("nop");
}
/* Write to this block to initiate precharge */
- *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
gd->ram_size = dramsize;
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
__asm__("nop");
/* Initialize DMR0 */
- dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
+ dramsize = (CFG_SYS_SDRAM_SIZE << 20);
temp = (dramsize - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, temp | 1);
__asm__("nop");
__asm__("nop");
/* Write to this block to initiate precharge */
- *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+ *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
mb();
__asm__("nop");
mbar_readLong(MCFSIM_DACR0) | 0x0040);
__asm__("nop");
- *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+ *(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
mb();
}
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
out_be16(&gpio_reg->par_sdram, 0x3FF);
/* Set up chip select */
- out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE);
out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
/* Set up timing */
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
/* Dummy write to start SDRAM */
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
setbits_be32(&sdp->sdmr,
MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
MCF_SDRAMC_SDMR_CMD);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
out_be32(&sdp->sdmr, 0x058d0000);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
out_be32(&sdp->sdmr, 0x018d0000);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
| MCF_SDRAMC_SDCR_DQS_OE(0x3));
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
{
u32 dramsize, i, dramclk;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
/* Initialize DACR0 */
MCFSDRAMC_DACR0 = (0
- | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
+ | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_32);
}
/* Write to this block to initiate precharge */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696;
asm("nop");
/* Set RE (bit 15) in DACR */
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
gd->ram_size = dramsize;
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CONFIG_SYS_SDRAM_BASE1
- out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+#ifdef CFG_SYS_SDRAM_BASE1
+ out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
#endif
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
asm("nop");
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
asm("nop");
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
asm("nop");
udelay(100);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
int fixed_sdram(void)
{
immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_SDRAM_SIZE;
+ u32 msize = CFG_SYS_SDRAM_SIZE;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
udelay(2000);
- return CONFIG_SYS_SDRAM_SIZE >> 20;
+ return CFG_SYS_SDRAM_SIZE >> 20;
}
#endif /*!CONFIG_SYS_SPD_EEPROM */
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freq_ddrbus));
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
/* u-boot dram initialize */
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
unsigned int reg_val = readl(SCR_USER_SIG6_READ);
/* set global data memory */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x00000100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
/* Number of Row: 14 bits */
if ((reg_val >> 28) == 14)
int board_init(void)
{
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
static long fixed_sdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_SDRAM_SIZE;
+ u32 msize = CFG_SYS_SDRAM_SIZE;
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_SDRAM_BASE & 0xfffff000);
+ CFG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
- return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+ return get_ram_size(CFG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
return 0;
{
DECLARE_GLOBAL_DATA_PTR;
- if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
+ if (gd->ram_top < CFG_SYS_SDRAM_BASE) {
/* 2GB wrapped around to 0 */
return CKSEG0ADDR(256 << 20);
}
/* setup basic address decode */
PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li t1, 0x0
- li t2, -CONFIG_SYS_SDRAM_SIZE
+ li t2, -CFG_SYS_SDRAM_SIZE
sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
/* setup PCI_BAR0 memory window */
- li t1, -CONFIG_SYS_SDRAM_SIZE
+ li t1, -CFG_SYS_SDRAM_SIZE
sw t1, MSC01_PCI_BAR0_OFS(t0)
/* setup PCI to SysCon/CPU translation */
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
{
/* MIG IP block is smart and doesn't need SW
* to do any init */
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */
+ gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */
return 0;
}
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 1 << 30);
return 0;
}
*/
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
char envval[16];
char *p;
- pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+ pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
sprintf(envval, "0x%x", pnvramaddr);
env_set("pnvramaddr", envval);
CONFIG_KM_PNVRAM) / 0x400;
env_set_ulong("pram", pram);
- varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+ varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
env_set_hex("varaddr", varaddr);
sprintf(envval, "0x%x", varaddr);
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
disable_addr_trans();
- msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+ msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
enable_addr_trans();
msize /= (1024 * 1024);
- if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) {
+ if (CFG_SYS_SDRAM_SIZE >> 20 != msize) {
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size >> 1, ddr_size_log2++)
return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
+ CFG_SYS_SDRAM_BASE & LAWBAR_BAR);
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
{
/* Define only 1MiB range for mem_regions at the middle of the RAM */
/* For 1GiB range mem_regions takes approx. 4min */
- *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
+ *vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
*size = 1 << 20;
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if !CONFIG_IS_ENABLED(DM_SPI)
vinco_spi0_hw_init();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
debug("gd->fdt_blob is %p\n", gd->fdt_blob);
return 0;
ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
0);
/* Detect memory physically present */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
/* Reconfigure memory for actual detected size */
*/
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
ddr_init();
gd->mem_clk = 0;
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000);
sec_init();
debug("PBF relocate done\n");
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
int board_init(void)
{
- gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+ gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
cpld_init();
/* arch number of AT91SAM9M10G45EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
pm9g45_nand_hw_init();
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
return 0;
}
u32 addr;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
}
return 0;
u32 addr, size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
gd->bd->bi_dram[i].start = addr;
unsigned long addr;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
}
return 0;
unsigned long addr, size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
gd->bd->bi_dram[i].start = addr;
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
int init_addr_map(void)
{
if (IS_ENABLED(CONFIG_ADDR_MAP))
- addrmap_set_entry(0, 0, CONFIG_SYS_SDRAM_SIZE, 0);
+ addrmap_set_entry(0, 0, CFG_SYS_SDRAM_SIZE, 0);
return 0;
}
#ifdef CONFIG_MACH_TYPE
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FACTORYSET
factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR);
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* we have to request the gpios again after relocation */
corvus_request_gpio();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
dram_init();
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
/* Bank 1 declares the memory available in the DDR high region */
#endif
/* Adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
smartweb_nand_hw_init();
smartweb_macb_hw_init();
int dram_init(void)
{
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ (void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
sdramc_configure(AT91_SDRAMC_NC_10);
/* Do memtest for 128MB */
- ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
/*
* If 32MB or 16MB should be supported check also for
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
taurus_request_gpio();
#ifdef CONFIG_CMD_NAND
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
phys_size_t get_effective_memsize(void)
{
- return CONFIG_SYS_SDRAM_SIZE;
+ return CFG_SYS_SDRAM_SIZE;
}
static int sram_init(void)
asm ("sync; isync; msync");
udelay(1000);
- if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
+ if (get_ram_size(0, CFG_SYS_SDRAM_SIZE<<20) == CFG_SYS_SDRAM_SIZE<<20) {
/*
* OK, size detected -> all done
*/
- return CONFIG_SYS_SDRAM_SIZE<<20;
+ return CFG_SYS_SDRAM_SIZE<<20;
}
return 0; /* nothing found ! */
status_led_set(2, CONFIG_LED_STATUS_ON);
/* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
if (!ret)
{
u32 max_size = imx_ddr_size();
- gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size_stride_test((u32 *) CFG_SYS_SDRAM_BASE,
(u32)max_size);
return 0;
int ret = 0;
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_VIDEO_IPUV3
ret = setup_display();
*/
out_be32(&dc->dacr0, 0x00003304);
- dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
+ dramsize = ((CFG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
out_be32(&dc->dmr0, dramsize|1);
/* issue a PRECHARGE ALL */
out_be32(&dc->dacr0, 0x0000b344);
out_be32((u32 *)0x00000c00, 0xbeaddeed);
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size(CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
gd->ram_size = dramsize;
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_VIDEO_IPUV3
setup_display();
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
modena_init0_bw_integer, modena_init0_watermark_0;
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
/*
int board_init(void)
{
gpmc_init();
- gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+ gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
return 0;
}
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
ram_size = board_ti_get_emif_size();
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
if (ram_size > CONFIG_MAX_MEM_MAPPED) {
gd->bd->bi_dram[1].start = 0x200000000;
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x7fffffff;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x37fffffff;
gd->ram_size = 0x400000000;
#endif
ddr3_size = ddr3_init();
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF)
if (!(board_is_k2g_ice() || board_is_k2g_i1()))
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
/* adjust memory start address for LPAE */
if (lpae) {
- start[0] -= CONFIG_SYS_SDRAM_BASE;
+ start[0] -= CFG_SYS_SDRAM_BASE;
start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
}
"linux,initrd-end", NULL);
if (prop1 && prop2) {
initrd_start = __be64_to_cpu(*prop1);
- initrd_start -= CONFIG_SYS_SDRAM_BASE;
+ initrd_start -= CFG_SYS_SDRAM_BASE;
initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_start = __cpu_to_be64(initrd_start);
initrd_end = __be64_to_cpu(*prop2);
- initrd_end -= CONFIG_SYS_SDRAM_BASE;
+ initrd_end -= CFG_SYS_SDRAM_BASE;
initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_end = __cpu_to_be64(initrd_end);
*reserve_start = __cpu_to_be64(*reserve_start);
size = __cpu_to_be64(*(reserve_start + 1));
if (size) {
- *reserve_start -= CONFIG_SYS_SDRAM_BASE;
+ *reserve_start -= CFG_SYS_SDRAM_BASE;
*reserve_start +=
CONFIG_SYS_LPAE_SDRAM_BASE;
*reserve_start =
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_SYS_FLASH_CFI
/* Use 16-bit memory interface for NOR Flash */
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int dram_init(void)
{
/* use the DDR controllers configured size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
(ulong)imx_ddr_size());
return 0;
int dram_init(void)
{
/* use the DDR controllers configured size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
(ulong)imx_ddr_size());
return 0;
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
{
reset_periph();
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
return board_late_init_xilinx();
}
-#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
#else
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
zynq_ddrc_init();
return ret;
}
-#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
int ret;
#else
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
mem_map_fill();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
return tmp;
}
-#if defined(CONFIG_SYS_SDRAM_BASE)
- return CONFIG_SYS_SDRAM_BASE;
+#if defined(CFG_SYS_SDRAM_BASE)
+ return CFG_SYS_SDRAM_BASE;
#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV)
return gd->bd->bi_dram[0].start;
#else
#ifdef CONFIG_ARCH_KEYSTONE
#include <asm/arch/ddr3.h>
-#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
+#define DDR_MIN_ADDR CFG_SYS_SDRAM_BASE
#define STACKSIZE (512 << 10) /* 512 KiB */
#define DDR_REMAP_ADDR 0x80000000
/* Check in ecc address range 1 */
if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) {
start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
- + CONFIG_SYS_SDRAM_BASE;
+ + CFG_SYS_SDRAM_BASE;
end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
- CONFIG_SYS_SDRAM_BASE;
+ CFG_SYS_SDRAM_BASE;
if ((addr >= start_addr) && (addr <= end_addr))
/* addr within ecc address range 1 */
return 1;
if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) {
range = readl(&emif->emif_ecc_address_range_2);
start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
- + CONFIG_SYS_SDRAM_BASE;
+ + CFG_SYS_SDRAM_BASE;
end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
- CONFIG_SYS_SDRAM_BASE;
+ CFG_SYS_SDRAM_BASE;
if ((addr >= start_addr) && (addr <= end_addr))
/* addr within ecc address range 2 */
return 1;
start_addr = hextoul(argv[2], NULL);
end_addr = hextoul(argv[3], NULL);
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
+ if ((start_addr < CFG_SYS_SDRAM_BASE) ||
+ (start_addr > (CFG_SYS_SDRAM_BASE +
get_effective_memsize() - 1)) ||
- (end_addr < CONFIG_SYS_SDRAM_BASE) ||
- (end_addr > (CONFIG_SYS_SDRAM_BASE +
+ (end_addr < CFG_SYS_SDRAM_BASE) ||
+ (end_addr > (CFG_SYS_SDRAM_BASE +
get_effective_memsize() - 1)) || (start_addr >= end_addr)) {
puts("Invalid start or end address!\n");
return cmd_usage(cmdtp);
/* Get the top of usable RAM */
__weak phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
-#if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
+#if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0
/*
* Detect whether we have so much RAM that it goes past the end of our
* 32-bit address space. If so, clip the usable RAM so it doesn't.
*/
- if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
+ if (gd->ram_top < CFG_SYS_SDRAM_BASE)
/*
* Will wrap back to top of 32-bit space when reservations
* are made.
*/
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
#endif
-#ifdef CONFIG_SYS_SDRAM_BASE
- gd->ram_base = CONFIG_SYS_SDRAM_BASE;
+#ifdef CFG_SYS_SDRAM_BASE
+ gd->ram_base = CFG_SYS_SDRAM_BASE;
#endif
gd->ram_top = gd->ram_base + get_effective_memsize();
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
cache-related registers config
CONFIG_SYS_CACHE_ACRX:
cache-related registers config
-CONFIG_SYS_SDRAM_BASE:
+CFG_SYS_SDRAM_BASE:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_SIZE:
+CFG_SYS_SDRAM_SIZE:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_BASEX:
+CFG_SYS_SDRAM_BASEX:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CFG1:
+CFG_SYS_SDRAM_CFG1:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CFG2:
+CFG_SYS_SDRAM_CFG2:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CTRL:
+CFG_SYS_SDRAM_CTRL:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_MODE:
+CFG_SYS_SDRAM_MODE:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_EMOD:
+CFG_SYS_SDRAM_EMOD:
SDRAM config for SDRAM controller-specific registers, please
see arch/m68k/cpu/<specific_cpu>/start.S files to see how
these options are used.
.. code-block:: c
- #define CONFIG_SYS_SDRAM_BASE 0xc8000000
- #define CONFIG_SYS_SDRAM_SIZE 0x08000000
+ #define CFG_SYS_SDRAM_BASE 0xc8000000
+ #define CFG_SYS_SDRAM_SIZE 0x08000000
You will need to change the environment variables location and setting,
too. You may change other configs to fit your board.
if (is_warm_boot()) {
ddr_out32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
- ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */
if (is_warm_boot()) {
ddr_out32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
- ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */
*/
#ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
#ifdef CONFIG_MPC83xx
-#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE
#else
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
#endif
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
- out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */
#define FAR_END_DIMM_ADDR 0x50
#define MAX_DIMM_ADDR 0x60
-#ifndef CONFIG_SYS_SDRAM_SIZE
+#ifndef CFG_SYS_SDRAM_SIZE
#define SDRAM_CS_SIZE 0xFFFFFFF
#else
-#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1)
+#define SDRAM_CS_SIZE ((CFG_SYS_SDRAM_SIZE >> 10) - 1)
#endif
#define SDRAM_CS_BASE 0x0
#define SDRAM_DIMM_SIZE 0x80000000
instead of a physical address (e.g. on MIPS). The PCI core will then remap
the virtual memory base address to a physical address when adding the PCI
region of type PCI_REGION_SYS_MEMORY.
- This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still
+ This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still
being used as virtual address.
config PCI_SRIOV
/* AHB-PCI Bridge Communication Registers */
writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG);
- writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
+ writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG);
writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16,
priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG);
/* PCI Configuration Registers for AHBPCI */
devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0);
writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0);
- writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
+ writel(CFG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
writel(0xf0000000, devad + PCI_BASE_ADDRESS_2);
writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
/* Set up target memory mappings (for external DMA access) */
/* Map both P0 and P2 range to Area 3 RAM for ease of use */
- p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
- p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
- p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
+ p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
+ p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
+ p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
p4_out(0, SH7751_PCILSR1);
p4_out(0, SH7751_PCILAR1);
}
/* Set the BAR base and size towards DDR */
- bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
+ bar0 = CFG_SYS_SDRAM_BASE & ~0xf;
bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
- writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
+ writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
reg = ((size >> 20) - 1) << 12;
writel(size, regs_base + RESIZABLE_BAR_CTL0);
#include <asm/arch-ls102xa/svr.h>
#ifndef CFG_SYS_PCI_MEMORY_BUS
-#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_PCI_MEMORY_BUS CFG_SYS_SDRAM_BASE
#endif
#ifndef CFG_SYS_PCI_MEMORY_PHYS
-#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_PCI_MEMORY_PHYS CFG_SYS_SDRAM_BASE
#endif
#ifndef CFG_SYS_PCI_MEMORY_SIZE
u32 test_pattern = 0xdeadbeef;
u32 cap_param = SDRAM_CONF_CAP_1024M;
u32 refresh_timing_param = DDR4_TRFC;
- const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
+ const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
ram_size >>= 1) {
((refresh_timing_param & SDRAM_AC_TRFC_MASK)
<< SDRAM_AC_TRFC_SHIFT));
- info->info.base = CONFIG_SYS_SDRAM_BASE;
+ info->info.base = CFG_SYS_SDRAM_BASE;
info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
clrsetbits_le32(&info->regs->config,
(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
u32 test_pattern = 0xdeadbeef;
u32 cap_param = SDRAM_CONF_CAP_2048M;
u32 refresh_timing_param = DDR4_TRFC;
- const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
+ const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
ram_size >>= 1) {
((refresh_timing_param & SDRAM_AC_TRFC_MASK)
<< SDRAM_AC_TRFC_SHIFT));
- info->info.base = CONFIG_SYS_SDRAM_BASE;
+ info->info.base = CFG_SYS_SDRAM_BASE;
info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK,
break;
}
- info->info.base = CONFIG_SYS_SDRAM_BASE;
+ info->info.base = CFG_SYS_SDRAM_BASE;
info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
if (0 == (conf & SDRAM_CONF_ECC_SETUP))
* and it has maximum addressing region
*/
- writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE);
+ writel(WALKING_PATTERN, CFG_SYS_SDRAM_BASE);
- if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN)
+ if (readl(CFG_SYS_SDRAM_BASE) != WALKING_PATTERN)
return -EINVAL;
for (step = 0; step < 5; step++) {
- writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE +
+ writel(~WALKING_PATTERN, CFG_SYS_SDRAM_BASE +
(WALKING_STEP << step));
- start = readl(CONFIG_SYS_SDRAM_BASE);
- test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step));
+ start = readl(CFG_SYS_SDRAM_BASE);
+ test = readl(CFG_SYS_SDRAM_BASE + (WALKING_STEP << step));
if ((test != ~WALKING_PATTERN) || test == start)
break;
}
struct mtk_ddr3_priv *priv = dev_get_priv(dev);
u32 val = readl(priv->emi + EMI_CONA);
- info->base = CONFIG_SYS_SDRAM_BASE;
+ info->base = CFG_SYS_SDRAM_BASE;
switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) {
case 0:
if (!mem_mbytes)
return -ENODEV;
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = MB(mem_mbytes);
/*
/* Detect col */
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + params->chan.bw - 1));
writel(test_pattern, addr);
if ((readl(addr) == test_pattern) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
/* Detect row*/
for (row = 16; row >= 12; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(test_pattern, addr);
if ((readl(addr) == test_pattern) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
u32 bw = cap_info->bw;
for (col = coltmp; col >= 9; col -= 1) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (col + bw - 1ul)));
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
u32 bk;
u32 bw = cap_info->bw;
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (coltmp + bktmp + bw - 1ul)));
- writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0, CFG_SYS_SDRAM_BASE);
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
bk = 3;
else
bk = 2;
u32 dbw;
u32 bw = cap_info->bw;
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (coltmp + bw + 1ul)));
- writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0, CFG_SYS_SDRAM_BASE);
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
dbw = 0;
else
dbw = 1;
void __iomem *test_addr;
for (row = rowtmp; row > 12; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (row + bktmp + coltmp + bw - 1ul)));
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
u32 row = cap_info->cs0_row;
void __iomem *test_addr, *test_addr1;
- test_addr = CONFIG_SYS_SDRAM_BASE;
- test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ test_addr = CFG_SYS_SDRAM_BASE;
+ test_addr1 = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
writel(0, test_addr);
/* detect cs1 row */
for (row = cap_info->cs0_row; row > 12; row--) {
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
cs0_cap +
(1ul << (row + bktmp + coltmp + bw - 1ul)));
- writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap);
+ writel(0, CFG_SYS_SDRAM_BASE + cs0_cap);
writel(PATTERN, test_addr);
if (((readl(test_addr) & byte_mask) ==
(PATTERN & byte_mask)) &&
- ((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) &
+ ((readl(CFG_SYS_SDRAM_BASE + cs0_cap) &
byte_mask) == 0)) {
break;
}
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: grf=%p\n", __func__, priv->pmugrf);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
/* Detect col. */
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTERN, addr);
if ((readl(addr) == TEST_PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
rk3066_dmc_move_to_access_state(chan);
/* Detect row, max 15, min13 for rk3066 */
for (row = 16; row >= 13; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTERN, addr);
if ((readl(addr) == TEST_PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
if (ret)
return ret;
} else {
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]);
}
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
debug("%s: grf=%p\n", __func__, priv->grf);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[1]);
/* Detect col */
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
move_to_access_state(chan);
/* Detect row, max 15,min13 in rk3188*/
for (row = 16; row >= 13; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
if (ret)
return ret;
#else
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->pmu->sys_reg[2]);
#endif
writel(3, &axi_bus->ddrconf);
move_to_access_state(dram->chan[0].pctl);
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
/* Detect row*/
for (row = 16; row >= 12; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 11) {
sdram_params->ch[0].cs0_row = row;
}
/* cs detect */
- writel(0, CONFIG_SYS_SDRAM_BASE);
- writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30));
- writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4);
- if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ writel(0, CFG_SYS_SDRAM_BASE);
+ writel(TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30));
+ writel(~TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30) + 4);
+ if ((readl(CFG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
sdram_params->ch[0].rank = 2;
else
sdram_params->ch[0].rank = 1;
if (ret)
return ret;
#else
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[2]);
#endif
/* Detect col */
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
move_to_access_state(chan);
/* Detect row*/
for (row = 16; row >= 12; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 11) {
if (ret)
return ret;
#else
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->pmu->sys_reg[2]);
#endif
struct dram_info *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2);
return 0;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
debug("%s: grf=%p\n", __func__, priv->grf);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[2]);
#endif
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
#endif
struct dram_info *priv = dev_get_priv(dev);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);
/* AHB-PCI Bridge Communication Registers */
writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
- writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
+ writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
&ahbcom_pci->pciahb_win1_ctr);
writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
&ahbcom_pci->pciahb_win2_ctr);
writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
&ahbcom_pci->ahbpci_win1_ctr);
writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
- writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
+ writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
writel(0xf0000000, &ahbconf_pci->win2_basead);
writel(SERREN | PERREN | MASTEREN | MEMEN,
&ahbconf_pci->cmnd_sts);
(struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS);
- writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
+ writel(CFG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
writel(mode->xres * 4, &de_fe->ch0_stride);
writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt);
writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt);
EFI_RESERVED_MEMORY_TYPE);
#endif
- fb_dma_addr = sunxi_display->fb_addr - CONFIG_SYS_SDRAM_BASE;
+ fb_dma_addr = sunxi_display->fb_addr - CFG_SYS_SDRAM_BASE;
if (overscan_offset) {
fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
sunxi_display->fb_addr += ALIGN(overscan_offset, 0x1000);
* -The heap is placed below the monitor
* -The stack is placed below the heap (&grows down).
*/
-#define CONFIG_SYS_SDRAM_BASE 0xc8000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0xc8000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
#endif /* __CONFIG_H */
* -The heap is placed below the monitor
* -The stack is placed below the heap (&grows down).
*/
-#define CONFIG_SYS_SDRAM_BASE 0xD0000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0xD0000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
#endif /* __CONFIG_H */
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x43711630
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
-#define CONFIG_SYS_SDRAM_EMOD 0x80010000
-#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1 0x43711630
+#define CFG_SYS_SDRAM_CFG2 0x56670000
+#define CFG_SYS_SDRAM_CTRL 0xE1002000
+#define CFG_SYS_SDRAM_EMOD 0x80010000
+#define CFG_SYS_SDRAM_MODE 0x00CD0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#ifdef CONFIG_SYS_FLASH_CFI
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/*
* For booting Linux, the board info and command line data
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DCM | \
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#if 0 /* test-only */
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(8) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
/*
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*
* FLASH organization
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
/*
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x43711630
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD 0x80010000
-#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1 0x43711630
+#define CFG_SYS_SDRAM_CFG2 0x56670000
+#define CFG_SYS_SDRAM_CTRL 0xE1092000
+#define CFG_SYS_SDRAM_EMOD 0x80010000
+#define CFG_SYS_SDRAM_MODE 0x00CD0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x53722730
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD 0x40010000
-#define CONFIG_SYS_SDRAM_MODE 0x018D0000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1 0x53722730
+#define CFG_SYS_SDRAM_CFG2 0x56670000
+#define CFG_SYS_SDRAM_CTRL 0xE1092000
+#define CFG_SYS_SDRAM_EMOD 0x40010000
+#define CFG_SYS_SDRAM_MODE 0x018D0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x53722730
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD 0x40010000
-#define CONFIG_SYS_SDRAM_MODE 0x018D0000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1 0x53722730
+#define CFG_SYS_SDRAM_CFG2 0x56670000
+#define CFG_SYS_SDRAM_CTRL 0xE1092000
+#define CFG_SYS_SDRAM_EMOD 0x40010000
+#define CFG_SYS_SDRAM_MODE 0x018D0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
-/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
+#define CFG_SYS_SDRAM_BASE 0x00000000
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE
/*
* DDR Setup
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
/*
* Manually set up DDR parameters
*/
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
+#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
#ifndef __ASSEMBLY__
extern unsigned long get_sdram_size(void);
#endif
-#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
+#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x52
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* Local Bus Definitions
#define _CONFIG_SBX81LIFKW_H
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration
#define _CONFIG_SBX81LIFXCAT_H
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_SDRAM_SIZE 2048
+#define CFG_SYS_SDRAM_SIZE 2048
#endif
/*
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
#define SPD_EEPROM_ADDRESS2 0x54
#define SPD_EEPROM_ADDRESS3 0x56
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions
#include <environment/ti/mmc.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
/* size of internal SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 0x1000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_FLASH_BASE 0xffc00000
/* amcore design has flash data bytes wired swapped */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
#define CFG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifndef __CONFIG_ARBEL_H
#define __CONFIG_ARBEL_H
-#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Misc CPU related */
-#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
+#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#ifdef CONFIG_PRE_CON_BUF_SZ
#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
/*
* Define baudrate for UART1 (console output, tftp, ...)
* (Set up by the startup code)
* for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/*
* Chipselect bank definitions
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
- (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
+ (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#ifdef CONFIG_AT91SAM9XE
#include <asm/hardware.h>
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x70000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0x70000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
/* DataFlash */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
*/
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* DataFlash */
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0
/*
* Serial console configuration
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_512M
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_512M
/*
* UART configuration
#ifndef __BCM947622_H
#define __BCM947622_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define COUNTER_FREQUENCY 50000000
#endif
#ifndef __BCM94908_H
#define __BCM94908_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM94912_H
#define __BCM94912_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM963138_H
#define __BCM963138_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_HZ_CLOCK 500000000
#endif
#ifndef __BCM963146_H
#define __BCM963146_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM963148_H
#define __BCM963148_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM963158_H
#define __BCM963158_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM963178_H
#define __BCM963178_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM96756_H
#define __BCM96756_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM96813_H
#define __BCM96813_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM96846_H
#define __BCM96846_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM96855_H
#define __BCM96855_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM96856_H
#define __BCM96856_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM96858_H
#define __BCM96858_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#ifndef __BCM96878_H
#define __BCM96878_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
#define V2M_BASE 0x80000000
#define PHYS_SDRAM_1 V2M_BASE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* Initial SP before reloaction is placed at end of first DRAM bank,
* MiB. However, BOLT can be configured to allow loading larger
* initramfs images, in which case this limitation is eliminated.
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
/*
#ifndef __CONFIG_BITMAIN_ANTMINER_S9_H
#define __CONFIG_BITMAIN_ANTMINER_S9_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"pxefile_addr_r=0x2000000\0" \
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (SZ_512M)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
* Memory map
*/
#ifdef CONFIG_64BIT
-# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+# define CFG_SYS_SDRAM_BASE 0xffffffff80000000
#else
-# define CONFIG_SYS_SDRAM_BASE 0x80000000
+# define CFG_SYS_SDRAM_BASE 0x80000000
#endif
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
* always, even when we have more. We always start at 0x80000000,
* and we place the initial stack pointer in our SRAM.
*/
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/*
* Our platforms make use of SPL to initalize the hardware (primarily
/* On CCP board, USDHC1 is for eMMC */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
/* DDR3 board total DDR is 1 GB */
#define CFG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
/* Memory configuration */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
+#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* NS16550-ish UARTs */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
*/
#define CONFIG_SYS_CLK 66000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/* ---
* Define baudrate for UART1 (console output, tftp, ...)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/*
*-------------------------------------------------------------------------
*-----------------------------------------------------------------------
*/
-/* #define CONFIG_SYS_SDRAM_SIZE 16 */
+/* #define CFG_SYS_SDRAM_SIZE 16 */
/*
*-----------------------------------------------------------------------
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
#define CFG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (256 * SZ_1M)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define PHYS_SDRAM_1 (V2M_BASE)
#define PHYS_SDRAM_1_SIZE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0)
#define CONFIG_USART_ID ATMEL_ID_SYS
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6
+#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
/* Load U-Boot Image From MMC */
/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_512M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/*
* Memory configurations
*/
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_64M
+#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_64M
/*
* DMA
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define PHYS_SDRAM_1 0x80000000
/* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */
#define PHYS_SDRAM_1_SIZE SZ_1G
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Environment */
#define BOOT_TARGET_DEVICES(func) \
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE 0x5ea4ffff
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#include <config_distro_bootcmd.h>
/* Sdram Bank #1 Address */
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE 0x7B000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* BOOT */
/*
* RAM
*/
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
/*
* cmd
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE0 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE0 0x00000000
+#define CFG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
-#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
+#define CFG_SYS_SDRAM_BASE CFG_SYS_SDRAM_BASE0
+#define CFG_SYS_SDRAM_SIZE CFG_SYS_SDRAM_SIZE0
/*
* For booting Linux, the board info and command line data
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x10000000
-#define CONFIG_SYS_SDRAM_SIZE SZ_16M
+#define CFG_SYS_SDRAM_BASE 0x10000000
+#define CFG_SYS_SDRAM_SIZE SZ_16M
/*
* Environment
#include <configs/exynos7420-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10)
/* 128MB SDRAM in 1 bank */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE (128 << 20)
/* 512kB on-chip NOR flash */
# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
#define CONFIG_RD_LVL
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
/* SPI */
#ifndef __CONFIG_5250_H
#define __CONFIG_5250_H
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
/* select serial console configuration */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
/* Configuration of ENV Blocks */
#define CONFIG_SYS_BAUDRATE_TABLE \
{9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_9 (CFG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_10 (CFG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_11 (CFG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_12 (CFG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
#ifndef MEM_LAYOUT_ENV_SETTINGS
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NAND flash */
#define CFG_SYS_NAND_BASE 0x40000000
#define __CONFIG_GARDENA_SMART_GATEWAY_H
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/*
* DDR Setup
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+/* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */
+#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE
/*
* Memory test
/* Memory */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Miscellaneous */
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
/* Network interface */
#define CONFIG_SH_ETHER_USE_PORT 0
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifndef _GXP_H_
#define _GXP_H_
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#endif
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x20000000\0" \
/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/
#define PHYS_SDRAM_1_SIZE 0x3EFFFFFF
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define PHYS_SDRAM_1 0x00000000
#define PHYS_SDRAM_1_SIZE 0xC0000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_1G
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_1G
/*
* UART configuration
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_1G
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_1G
/*
* UART configuration
*/
/* SDRAM Configuration (for final code, data, stack, heap) */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
/*----------------------------------------------------------------------
* Commands
"upd=run load update\0" \
/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#endif /* __IMX27LITE_COMMON_CONFIG_H */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_128M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR)
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */
/* Totally 2GB DDR */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
/* Totally 6GB or 4G DDR */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
*/
#define CFG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
*/
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* FLASH and environment organization
* : :
* : Specified explicitly by CONFIG_CUSTOM_SYS_INIT_SP_ADDR
* :
- * Specified explicitly by CONFIG_SYS_SDRAM_BASE
+ * Specified explicitly by CFG_SYS_SDRAM_BASE
*
* NOTES:
* - Stack starts from CONFIG_CUSTOM_SYS_INIT_SP_ADDR and grows down,
- * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing
- * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on
+ * i.e. towards CFG_SYS_SDRAM_BASE but nothing stops it from crossing
+ * that CFG_SYS_SDRAM_BASE in which case data won't be really saved on
* stack any longer and values popped from stack will contain garbage
* leading to unexpected behavior, typically but not limited to:
* - "Returning" back to bogus caller function
#define DCCM_BASE 0x80000000
#define DCCM_SIZE SZ_128K
-#define CONFIG_SYS_SDRAM_BASE DCCM_BASE
-#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE
+#define CFG_SYS_SDRAM_BASE DCCM_BASE
+#define CFG_SYS_SDRAM_SIZE DCCM_SIZE
#define ROM_BASE CONFIG_SYS_MONITOR_BASE
#define ROM_SIZE SZ_256K
#define RAM_DATA_BASE SYS_INIT_SP_ADDR
-#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \
+#define RAM_DATA_SIZE CFG_SYS_SDRAM_SIZE - \
(SYS_INIT_SP_ADDR - \
- CONFIG_SYS_SDRAM_BASE) - \
+ CFG_SYS_SDRAM_BASE) - \
CONFIG_SYS_MALLOC_LEN - \
CONFIG_ENV_SIZE
#endif /* _CONFIG_IOT_DEVKIT_H_ */
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
/* FLASH Configuration */
#define CONFIG_SYS_FLASH_BASE 0x000000000
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
/*
* DDR Setup
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
/*
* Manually set up DDR parameters
*/
-#define CONFIG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */
+#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */
/*
* The reserved memory
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/******************************************************************************
* (PRAM usage)
/* RAM */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* RAM */
#define PHYS_SDRAM DDR_CSD1_BASE_ADDR
#define PHYS_SDRAM_SIZE (SZ_4G)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/* early stack pointer */
#define PHYS_SDRAM_1_SIZE (512 * SZ_1M)
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
"bootscript=source ${bootscraddr}\0"
/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */
#define __CONFIG_LINKIT_SMART_7688_H
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 0x40000000
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/*SPI device */
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 0x40000000
/*
* QIXIS Definitions
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 0x40000000
/*
* I2C IO expander
#define SDRAM_CFG_BI 0x00000001
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/*
* Serial Port
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Serial Port */
#define CFG_SYS_NS16550_CLK get_serial_clock()
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/*
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
* SMP Definitinos
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
-#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE 0x200000000UL
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
*/
#ifdef CONFIG_64BIT
-# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+# define CFG_SYS_SDRAM_BASE 0xffffffff80000000
#else
-# define CONFIG_SYS_SDRAM_BASE 0x80000000
+# define CFG_SYS_SDRAM_BASE 0x80000000
#endif
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
+#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
*/
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_SDRAM_SIZE SZ_1G
+#define CFG_SYS_SDRAM_SIZE SZ_1G
#endif /* _CONFIG_DB_MV7846MP_GP_H */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define STDIN_CFG "serial"
#endif
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
/* ROM USB boot support, auto-execute boot.scr at scriptaddr */
#define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define PHYS_SDRAM_2 0xc0000000
#ifndef __CONFIG_MT7620_H
#define __CONFIG_MT7620_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#ifndef __CONFIG_MT7621_H
#define __CONFIG_MT7621_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED 0x1c000000
/* SPL -> Uboot */
#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* Ethernet */
#define CONFIG_IPADDR 192.168.1.1
#define MMC_SUPPORTS_TUNING
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* This is needed for kernel booting */
#define FDT_HIGH "0xac000000"
#ifndef __CONFIG_MT7628_H
#define __CONFIG_MT7628_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
/* UBoot -> Kernel */
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* Ethernet */
#define CONFIG_IPADDR 192.168.1.1
#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#endif
#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#endif
#define __MT8518_H
/* DRAM definition */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* Uboot definition */
*/
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration
#include <asm/arch/soc.h>
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x200000000
+#define CFG_SYS_SDRAM_BASE 0x200000000
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
*/
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Status LED */
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Extra Environments */
#define CONFIG_EXTRA_ENV_SETTINGS \
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* UBI and NAND partitioning */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#include <config_distro_bootcmd.h>
/* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_2G
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM 0x60000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=zImage\0" \
#define PHYS_SDRAM 0x60000000
#define PHYS_SDRAM_SIZE SZ_1G
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
* FLASH and environment organization
*/
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
*/
#define SDRAM_SIZE 0x10000000 /* 256 MB */
-#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE)
+#define SDRAM_END (CFG_SYS_SDRAM_BASE + SDRAM_SIZE)
#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */
#define KERNEL_OFFSET 0x40000 /* 256 kB */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_256M
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_256M
/*
* Console configuration
#include "mx6_common.h"
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
#endif
-#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+#define CFG_SYS_SDRAM_BASE 0xffffffff80000000
#endif /* __OCTEON_COMMON_H__ */
/** Maximum size of image supported for bootm (and bootable FIT images) */
/** Memory base address */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
/** Stack starting address */
/** Maximum size of image supported for bootm (and bootable FIT images) */
/** Memory base address */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
/** Stack starting address */
#define CONFIG_SYS_PL310_BASE 0x10502000
#endif
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#include <linux/sizes.h>
#include <configs/exynos5420-common.h>
#include <configs/exynos5-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define TZPC_BASE_OFFSET 0x10000
/* defines for SPL */
/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>
#include <linux/sizes.h>
/* Environment options */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* ---------------------------------------------------------------------
* Board boot configuration
#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR
/* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#include <configs/exynos4-common.h>
/* ORIGEN has 4 bank of DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Power Down Modes */
#define _OWL_COMMON_CONFIG_H_
/* SDRAM Definitions */
-#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_SDRAM_BASE 0x0
/* Some commands use this as the default load address */
#define SPD_EEPROM_ADDRESS 0x52
#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
+#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
#else
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
+#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
#endif
-#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19))
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Default settings for DDR3 */
#ifndef CONFIG_TARGET_P2020RDB
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_POWER_TPS65090_EC
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE)
/* SDRAM Configuration (for final code, data, stack, heap) */
-#define CONFIG_SYS_SDRAM_BASE 0x88000000
+#define CFG_SYS_SDRAM_BASE 0x88000000
/* Memory Test */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
""
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#endif
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
""
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#endif
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x70000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0x70000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#endif
#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20)
-#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_SDRAM_BASE 0x0
/* Default environemnt variables */
#define CONFIG_SERVERIP 192.168.0.1
#define __POMELO_CONFIG_H__
/* SDRAM Bank #1 start address */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* SIZE of malloc pool */
#define DDR_BASE 0x00000000
#define PHYS_SDRAM_1 DDR_BASE
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Console I/O Buffer Size */
#define GICD_BASE 0xff131000
#define GICC_BASE 0xff132000
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define SDRAM_BANK_SIZE (2UL << 30)
/* Physical memory map */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* GUIDs for capsule updatable firmware images */
#define QEMU_ARM_UBOOT_IMAGE_GUID \
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_HWCONFIG
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
/* SCIF */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x8C000000
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE 0x8C000000
+#define CFG_SYS_SDRAM_SIZE 0x04000000
/* Address of u-boot image in Flash */
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* console */
#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
-#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
+#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
+#define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
/* Timer */
#define CONFIG_TMU_TIMER
/* MEMORY */
#define DRAM_RSV_SIZE 0x08000000
-#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
-#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_SYS_HZ_CLOCK 24000000
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
#define CONFIG_IRAM_BASE 0x10080000
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (1024UL << 20UL)
#define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_MAX_SIZE 0x80000000
/* usb mass storage */
/* spl size 32kb sram - 2kb bootrom */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (2UL << 30)
#define SDRAM_MAX_SIZE 0x80000000
#define CONFIG_IRAM_BASE 0x10080000
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE 0x80000000
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_BANK_SIZE (2UL << 30)
#define SDRAM_MAX_SIZE 0xfe000000
#define CONFIG_IRAM_BASE 0xfff80000
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define SDRAM_BANK_SIZE (2UL << 30)
#define CONFIG_IRAM_BASE 0xff090000
/* FAT sd card locations. */
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define ENV_MEM_LAYOUT_SETTINGS \
#include <asm/arch-rockchip/hardware.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_IRAM_BASE 0xff8c0000
/* RAW SD card / eMMC locations. */
/* FAT sd card locations. */
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf8000000
#ifndef CONFIG_SPL_BUILD
#define CONFIG_IRAM_BASE 0xfdcc0000
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf0000000
#define ENV_MEM_LAYOUT_SETTINGS \
#endif
/* Memory layout */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/*
* The board really has 256M. However, the VC (VideoCore co-processor) shares
* smaller amount of RAM is present in order to avoid stomping on the area
* the VC uses.
*/
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CFG_SYS_SDRAM_SIZE SZ_128M
/* Devices */
/* LCD */
#define CONFIG_SYS_TIMER_BASE 0x10350020
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
/* rockchip ohci host driver */
/*-----------------------------------------------------------------------
* System memory Configuration
*/
-#define CONFIG_SYS_SDRAM_BASE 0x71000000
+#define CFG_SYS_SDRAM_BASE 0x71000000
/*
* "(0x40000000 - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in
* Starting kernel ...
* ...
*/
-#define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_SDRAM_SIZE (0xb0000000 - CFG_SYS_SDRAM_BASE)
#define BMP_LOAD_ADDR 0x78000000
#include <asm/arch/cpu.h> /* get chip and board defs */
/* DRAM Base */
-#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CFG_SYS_SDRAM_BASE 0x30000000
/* Text Base */
"dfu_alt_info=" CONFIG_DFU_ALT "\0"
/* Goni has 3 banks of DRAM, but swap the bank */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
#define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */
#define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */
#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */
/* Keep L2 Cache Disabled */
/* Universal has 2 banks of DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_USART_ID 0 /* ignored in arm */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */
#endif
*/
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000
/* SPL */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SD_BOOT
/* u-boot env in sd/mmc card */
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* NAND Flash */
#ifdef CONFIG_CMD_NAND
#define ATMEL_PMC_UHP (1 << 6)
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#endif
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* SerialFlash */
#include "at91-sama5_common.h"
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#include "at91-sama5_common.h"
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
#endif
/* Size of our emulated memory */
#define SB_CONCAT(x, y) x ## y
#define SB_TO_UL(s) SB_CONCAT(s, UL)
-#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_SDRAM_SIZE \
+#define CFG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_SIZE \
(SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
/* Physical Memory Map */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
-#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_DRAM_1
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_SIZE SZ_8M
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_SIZE SZ_8M
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
* SDRAM: 1 bank, 64 MB, base address 0x20000000
* Already initialized before u-boot gets started.
*/
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M)
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE (64 * SZ_1M)
/*
* Perform a SDRAM Memtest from the start of SDRAM
#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
/* input clock of PLL: SMDKC100 has 12MHz input clock */
/* DRAM Base */
-#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CFG_SYS_SDRAM_BASE 0x30000000
/* Text Base */
*/
/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */
/*-----------------------------------------------------------------------
#include "exynos4-common.h"
/* High Level Configuration Options */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* Handling Sleep Mode*/
#define S5P_CHECK_SLEEP 0x00000BAD
/* SMDKV310 has 4 bank of DRAM */
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
/* FLASH and environment organization */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* CPU */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
-#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6
+#define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
* Memory
*/
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/*
* I2C
* in U-Boot pre-reloc is higher than in SPL.
*/
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* U-Boot general configurations
*/
#define PHYS_SDRAM_1 0x0
#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
/*
* Serial / UART configurations
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
/* I2C addresses of SPD EEPROMs */
#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
#define CONFIG_SYS_DDR_CONFIG 0xC3008000
#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
-#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
+#define CFG_SYS_SDRAM_SIZE 256 /* in Megs */
/*
* Flash on the LocalBus
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* ram memory-related information */
#define PHYS_SDRAM_1 0x40000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x3E000000
#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */
/*
* Configuration of the external SRAM memory used by U-Boot
*/
-#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
+#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
/*
* For booting Linux, use the first 256 MB of memory, since this is
/*
* Configuration of the external SRAM memory used by U-Boot
*/
-#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
+#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
/*
* For booting Linux, use the first 256 MB of memory, since this is
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
#define CONFIG_SYS_DRAM_TEST
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
- (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
+ (CFG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
CF_CACR_ICINVA | CF_CACR_EUSP)
/* ram memory-related information */
#define PHYS_SDRAM_1 0x00000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x00198000
/* user interface */
*/
#ifdef CONFIG_MACH_SUN9I
#define SDRAM_OFFSET(x) 0x2##x
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
#elif defined(CONFIG_MACH_SUNIV)
#define SDRAM_OFFSET(x) 0x8##x
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#else
#define SDRAM_OFFSET(x) 0x4##x
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* V3s do not have enough memory to place code at 0x4a000000 */
#endif
/* FIXME: this may be larger on some SoCs */
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
-#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
/* mmc config */
/*
* SDRAM (for initialize)
*/
-#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
+#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M)
/*
* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_128M
/*
* UART configuration
/* General configuration */
/* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
/* Defines for SPL */
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_SDRAM_SIZE SZ_2G
+#define CFG_SYS_SDRAM_SIZE SZ_2G
#endif /* _CONFIG_THEADORABLE_H */
/* Link Definitions */
/* SMP Spin Table Definitions */
-#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CPU_RELEASE_ADDR (CFG_SYS_SDRAM_BASE + 0x7fff0)
/* PL011 Serial Configuration */
/* Physical Memory Map */
#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Initial environment variables */
#define UBOOT_IMG_HEAD_SIZE 0x40
#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/**
* Platform/Board specific defs
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/**
* Platform/Board specific defs
* initial stack pointer in our SRAM. Otherwise, we can define
* CONFIG_NR_DRAM_BANKS before including this file.
*/
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* If DM_I2C, enable non-DM I2C support */
/* Top 48MB reserved for secure world use */
#define DRAM_SEC_SIZE 0x03000000
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_2 0x8080000000
#define PHYS_SDRAM_2_SIZE 0x180000000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0xa0000000
+#define CFG_SYS_SDRAM_BASE 0xa0000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif
/* TRATS has 4 banks of DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Tizen - partitions definitions */
#endif
/* TRATS2 has 4 banks of DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Tizen - partitions definitions */
#ifndef _CONFIG_TURRIS_MOX_H
#define _CONFIG_TURRIS_MOX_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
*/
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
#define PHYS_SDRAM CSD0_BASE_ADDR
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
-#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
+#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M)
#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
-#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M)
+#define CFG_SYS_SDRAM_SIZE (256 * SZ_1M)
#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
-#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M)
+#define CFG_SYS_SDRAM_SIZE (512 * SZ_1M)
#else
#error Unknown DDR size - please add!
#endif
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#endif
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
/* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G)
#define PHYS_SDRAM_2 0x100000000
/* Top 16MB reserved for secure world use */
#define DRAM_SEC_SIZE 0x01000000
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define PHYS_SDRAM_2 (0x880000000)
#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
/* additions for new relocation code */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
/* Basic environment settings */
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x4000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x4000000
/* MMC */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define __VOCORE2_CONFIG_H__
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/*
* Memory configurations
*/
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_128M
#define CONFIG_RTC_DS1374
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Extra Environment */
#define CONFIG_HOSTNAME "xea"
#define CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_SYS_SDRAM_BASE
+#undef CFG_SYS_SDRAM_BASE
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_SDRAM_SIZE 0x1000000
-#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_SDRAM_SIZE 0x1000000
+#define CFG_SYS_SDRAM_BASE 0x0
#endif /* __CONFIG_ZYNQMP_MINI_NAND_H */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (128 << 20)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
*/
#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
-#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
+#define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
#else
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000
#endif
-#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
+#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000)
/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
#endif
#if defined(CONFIG_MAX_MEM_MAPPED) && \
- CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
+ CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE
#define XTENSA_SYS_TEXT_ADDR \
(MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
#else
#define XTENSA_SYS_TEXT_ADDR \
- (MEMADDR(CONFIG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
+ (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
#endif
/*==============================*/
*
* If this is not provided, a default implementation will try to set up a
* single bank. It will do this if CONFIG_NR_DRAM_BANKS and
- * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
- * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
+ * CFG_SYS_SDRAM_BASE are set. The bank will have a start address of
+ * CFG_SYS_SDRAM_BASE and the size will be determined by a call to
* get_effective_memsize().
*
* Return: 0 if OK, -ve on error
#define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR
#else
#ifdef CONFIG_MIPS
-#define SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET)
+#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET)
#else
#define SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
{
struct bd_info *bd = gd->bd;
- *vstart = CONFIG_SYS_SDRAM_BASE;
+ *vstart = CFG_SYS_SDRAM_BASE;
*size = (gd->ram_size >= 256 << 20 ?
256 << 20 : gd->ram_size) - (1 << 20);
* at SDRAM_BASE *device* address (p_paddr field).
* Its size is defined by the p_filesz field.
*/
- phdr->p_paddr = CONFIG_SYS_SDRAM_BASE;
+ phdr->p_paddr = CFG_SYS_SDRAM_BASE;
loaded_firmware_size = phdr->p_filesz;
/*
unmap_physmem(loaded_firmware, MAP_NOCACHE);
/* Resource table */
- shdr->sh_addr = CONFIG_SYS_SDRAM_BASE;
+ shdr->sh_addr = CFG_SYS_SDRAM_BASE;
rsc_table_size = shdr->sh_size;
loaded_rsc_table_paddr = shdr->sh_addr + DEVICE_TO_PHYSICAL_OFFSET;
/* Load and verify */
ut_assertok(rproc_elf32_load_rsc_table(dev, (ulong)valid_elf32, size,
&rsc_addr, &rsc_size));
- ut_asserteq(rsc_addr, CONFIG_SYS_SDRAM_BASE);
+ ut_asserteq(rsc_addr, CFG_SYS_SDRAM_BASE);
ut_asserteq(rsc_size, rsc_table_size);
ut_asserteq_mem(loaded_firmware, valid_elf32 + shdr->sh_offset,
shdr->sh_size);
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