net/designware: Consecutive writes must have delay

This patch solves a TX/RX problem which happens at 10Mbps, due to the
fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between
two consecutive writes on the same register.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index fc14b70420615e4b89bbeb08dec9ee6e086c94d8..933032cfdef56b08300b4c88141e4e1a7a745d45 100644 (file)
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -175,8 +175,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
        writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
        writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
 
-       writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf);
-       writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf);
+       writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
 
        return 0;
 }