These boards have not been converted to CONFIG_DM_MMC by the deadline.
Remove them. As the P5020 is the last ARCH_P5020 platform, remove that
support as well.
Cc: Andy Fleming <afleming@gmail.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
imply CMD_SATA
imply PANIC_HANG
-config TARGET_CYRUS_P5020
- bool "Support Varisys Cyrus P5020"
- select ARCH_P5020
- select PHYS_64BIT
- imply PANIC_HANG
-
-config TARGET_CYRUS_P5040
- bool "Support Varisys Cyrus P5040"
- select ARCH_P5040
- select PHYS_64BIT
- imply PANIC_HANG
-
endchoice
config ARCH_B4420
imply CMD_REGINFO
imply SATA_SIL
-config ARCH_P5020
- bool
- select E500MC
- select FSL_LAW
- select SYS_FSL_DDR_VER_44
- select SYS_FSL_ERRATUM_A004510
- select SYS_FSL_ERRATUM_A005275
- select SYS_FSL_ERRATUM_A006261
- select SYS_FSL_ERRATUM_DDR_A003
- select SYS_FSL_ERRATUM_DDR_A003474
- select SYS_FSL_ERRATUM_ESDHC111
- select SYS_FSL_ERRATUM_I2C_A004447
- select SYS_FSL_ERRATUM_SRIO_A004034
- select SYS_FSL_ERRATUM_USB14
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_QORIQ_CHASSIS1
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select SYS_PPC64
- select FSL_ELBC
- imply CMD_SATA
- imply CMD_REGINFO
- imply FSL_SATA
-
config ARCH_P5040
bool
select E500MC
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020 || \
- ARCH_P5020 || \
ARCH_T1023 || \
ARCH_T1024
default 1
ARCH_P2041 || \
ARCH_P3041 || \
ARCH_P4080 || \
- ARCH_P5020 || \
ARCH_P5040 || \
ARCH_T1023 || \
ARCH_T1024 || \
default 0x00 if ARCH_MPC8548
default 0x10 if ARCH_P1010
default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
- default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
+ default 0x20 if ARCH_P3041 || ARCH_P4080
config SYS_FSL_ERRATUM_IFC_A002769
bool
ARCH_P2041 || \
ARCH_P3041 || \
ARCH_P4080 || \
- ARCH_P5020 || \
ARCH_P5040 || \
ARCH_T2080 || \
ARCH_T4160 || \
default 2 if ARCH_P2041 || \
ARCH_P3041 || \
ARCH_P4080 || \
- ARCH_P5020 || \
ARCH_P5040
default 1
source "board/keymile/Kconfig"
source "board/sbc8548/Kconfig"
source "board/socrates/Kconfig"
-source "board/varisys/cyrus/Kconfig"
source "board/xes/xpedite520x/Kconfig"
source "board/xes/xpedite537x/Kconfig"
source "board/xes/xpedite550x/Kconfig"
obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
-obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
-obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
- /* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO(1, 2, 1, 0),
- SET_QP_INFO(3, 4, 2, 1),
- SET_QP_INFO(5, 6, 3, 0),
- SET_QP_INFO(7, 8, 4, 1),
- SET_QP_INFO(9, 10, 5, 0),
- SET_QP_INFO(11, 12, 6, 1),
- SET_QP_INFO(13, 14, 7, 0),
- SET_QP_INFO(15, 16, 8, 1),
- SET_QP_INFO(17, 18, 9, 0),
- SET_QP_INFO(19, 20, 10, 1),
-};
-#endif
-
-struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_2(1, 199, 200),
- SET_SRIO_LIODN_2(2, 201, 202),
-};
-int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
-
-struct liodn_id_table liodn_tbl[] = {
-#ifdef CONFIG_SYS_DPAA_QBMAN
- SET_QMAN_LIODN(31),
- SET_BMAN_LIODN(32),
-#endif
-
- SET_SDHC_LIODN(1, 64),
-
- SET_PME_LIODN(117),
-
- SET_USB_LIODN(1, "fsl-usb2-mph", 125),
- SET_USB_LIODN(2, "fsl-usb2-dr", 126),
-
- SET_SATA_LIODN(1, 127),
- SET_SATA_LIODN(2, 128),
-
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
-
- SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
- SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
-
- SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
- SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
- SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
- SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
-};
-int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-struct fman_liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 10),
- SET_FMAN_RX_1G_LIODN(1, 1, 11),
- SET_FMAN_RX_1G_LIODN(1, 2, 12),
- SET_FMAN_RX_1G_LIODN(1, 3, 13),
- SET_FMAN_RX_1G_LIODN(1, 4, 14),
- SET_FMAN_RX_10G_LIODN(1, 0, 15),
-};
-int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-#endif
-
-struct liodn_id_table sec_liodn_tbl[] = {
- SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
- SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
- SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
- SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
- SET_SEC_RTIC_LIODN_ENTRY(a, 154),
- SET_SEC_RTIC_LIODN_ENTRY(b, 155),
- SET_SEC_RTIC_LIODN_ENTRY(c, 156),
- SET_SEC_RTIC_LIODN_ENTRY(d, 157),
- SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
- SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
-};
-int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
-
-#ifdef CONFIG_SYS_FSL_RAID_ENGINE
-struct liodn_id_table raide_liodn_tbl[] = {
- SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
- SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
- SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
- SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
-};
-int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_RMAN
-struct liodn_id_table rman_liodn_tbl[] = {
- /* Set RMan block 0-3 liodn offset */
- SET_RMAN_LIODN(0, 6),
- SET_RMAN_LIODN(1, 7),
- SET_RMAN_LIODN(2, 8),
- SET_RMAN_LIODN(3, 9),
-};
-int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
-#endif
-
-struct liodn_id_table liodn_bases[] = {
- [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
-#ifdef CONFIG_SYS_DPAA_FMAN
- [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
-#endif
-#ifdef CONFIG_SYS_DPAA_PME
- [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
-#endif
-#ifdef CONFIG_SYS_FSL_RAID_ENGINE
- [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47),
-#endif
-#ifdef CONFIG_SYS_DPAA_RMAN
- [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80),
-#endif
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_serdes.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "fsl_corenet_serdes.h"
-
-static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
- [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
- [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
- PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, },
- [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, },
- [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
- SRIO1, },
- [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
- NONE, NONE, },
- [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
- SATA1, SATA2, },
- [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, },
- [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, },
- [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
- NONE, NONE, },
- [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
- NONE, NONE, },
- [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, },
- [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
- NONE, NONE, },
- [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
- AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
- NONE, SATA1, SATA2, },
- [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
- [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
- AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
- NONE, SATA1, SATA2, },
- [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
-};
-
-enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
-{
- if (!serdes_lane_enabled(lane))
- return NONE;
-
- return serdes_cfg_tbl[cfg][lane];
-}
-
-int is_serdes_prtcl_valid(u32 prtcl) {
- int i;
-
- if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
- return 0;
-
- for (i = 0; i < SRDS_MAX_LANES; i++) {
- if (serdes_cfg_tbl[prtcl][i] != NONE)
- return 1;
- }
-
- return 0;
-}
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
-#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_NUM_FM1_DTSEC 5
-#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 32
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
-
#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#if defined(CONFIG_ARCH_P3041) || \
defined(CONFIG_ARCH_P4080) || \
- defined(CONFIG_ARCH_P5020) || \
defined(CONFIG_ARCH_P5040) || \
defined(CONFIG_ARCH_P2041)
#define CONFIG_FSL_TRUST_ARCH_v1
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
#endif
#if defined(CONFIG_ARCH_P2041) || \
- defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
+ defined(CONFIG_ARCH_P3041)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
+++ /dev/null
-if TARGET_CYRUS_P5020 || TARGET_CYRUS_P5040
-
-config SYS_BOARD
- default "cyrus"
-
-config SYS_VENDOR
- default "varisys"
-
-config SYS_CONFIG_NAME
- default "cyrus"
-
-source "board/freescale/common/Kconfig"
-
-endif
+++ /dev/null
-Cyrus BOARD
-M: Andy Fleming <afleming@gmail.com>
-S: Maintained
-F: board/varisys/cyrus/
-F: include/configs/cyrus.h
-F: configs/Cyrus_P5020_defconfig
-F: configs/Cyrus_P5040_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += $(BOARD).o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-obj-y += eth.o
-obj-$(CONFIG_PCI) += pci.o
+++ /dev/null
-Rebuilding u-boot for Cyrus
-
-The Cyrus defconfigs are Cyrus_P5020_defconfig and Cyrus_P5040_defconfig.
-
-They currently disable size optimization in order to avoid a relocation
-bug in some versions of GCC. As the output size is a constant, the size
-optimization is not currently important.
-
-Cyrus boots off a microSD card in a slot on the motherboard. This requires
-that the u-boot is built for the Pre-Boot Loader on the P5020/P5040.
-In order to reflash u-boot, you must download u-boot.pbl, then write it
-onto the card. To do that from u-boot:
-
-> tftp 1000000 u-boot.pbl
-> mmc write 1000000 8 672
-
-If you want to do this via a card reader in linux:
-
-> dd if=u-boot.pbl of=/dev/sdX bs=512 oseek=8
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Based on corenet_ds.c
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <pci.h>
-
-#include "cyrus.h"
-#include "../common/eeprom.h"
-
-#define GPIO_OPENDRAIN 0x30000000
-#define GPIO_DIR 0x3c000004
-#define GPIO_INITIAL 0x30000000
-#define GPIO_VGA_SWITCH 0x00001000
-
-int checkboard(void)
-{
- printf("Board: CYRUS\n");
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-
- /*
- * Only use DDR1_MCK0/3 and DDR2_MCK0/3
- * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
- * the noise introduced by these unterminated and unused clock pairs.
- */
- setbits_be32(&gur->ddrclkdr, 0x001B001B);
-
- /* Set GPIO reset lines to open-drain, tristate */
- setbits_be32(&pgpio->gpdat, GPIO_INITIAL);
- setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);
-
- /* Set GPIO Direction */
- setbits_be32(&pgpio->gpdir, GPIO_DIR);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- out_be32(&lbc->lbcr, 0);
- /* 1 clock LALE cycle */
- out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR);
-
- set_liodns();
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_qbman_portals();
-#endif
- print_lbc_regs();
- return 0;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
-#endif
-
- return 0;
-}
-
-int mac_read_from_eeprom(void)
-{
- init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,
- CONFIG_SYS_I2C_EEPROM_ADDR,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN);
-
- return mac_read_from_eeprom_common();
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef __CYRUS_H
-#define __CYRUS_H
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, struct bd_info *bd);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Based on corenet_ds ddr code
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | |delay |
- */
- {4, 850, 4, 6, 0xff, 2, 0},
- {4, 950, 5, 7, 0xff, 2, 0},
- {4, 1050, 5, 8, 0xff, 2, 0},
- {4, 1250, 5, 10, 0xff, 2, 0},
- {4, 1350, 5, 11, 0xff, 2, 0},
- {4, 1666, 5, 12, 0xff, 2, 0},
- {2, 850, 5, 6, 0xff, 2, 0},
- {2, 1050, 5, 7, 0xff, 2, 0},
- {2, 1250, 4, 6, 0xff, 2, 0},
- {2, 1350, 5, 7, 0xff, 2, 0},
- {2, 1666, 5, 8, 0xff, 2, 0},
- {1, 1250, 4, 6, 0xff, 2, 0},
- {1, 1335, 4, 7, 0xff, 2, 0},
- {1, 1666, 4, 8, 0xff, 2, 0},
- {}
-};
-
-/*
- * The two slots have slightly different timing. The center values are good
- * for both slots. We use identical speed tables for them. In future use, if
- * DIMMs have fewer center values that require two separated tables, copy the
- * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
- */
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm0,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | |delay |
- */
- {4, 850, 4, 6, 0xff, 2, 0},
- {4, 950, 5, 7, 0xff, 2, 0},
- {4, 1050, 5, 8, 0xff, 2, 0},
- {4, 1250, 5, 10, 0xff, 2, 0},
- {4, 1350, 5, 11, 0xff, 2, 0},
- {4, 1666, 5, 12, 0xff, 2, 0},
- {2, 850, 4, 6, 0xff, 2, 0},
- {2, 1050, 4, 7, 0xff, 2, 0},
- {2, 1666, 4, 8, 0xff, 2, 0},
- {1, 850, 4, 5, 0xff, 2, 0},
- {1, 950, 4, 7, 0xff, 2, 0},
- {1, 1666, 4, 8, 0xff, 2, 0},
- {}
-};
-
-/*
- * The two slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 60 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
- puts("Initializing....");
-
- if (!fsl_use_spd())
- panic("Cyrus only supports using SPD for DRAM\n");
-
- puts("using SPD\n");
- dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Author Adrian Cox
- * Based somewhat on board/freescale/corenet_ds/eth_hydra.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fdt_support.h>
-#include <fsl_dtsec.h>
-
-#ifdef CONFIG_FMAN_ENET
-
-#define FIRST_PORT_ADDR 3
-#define SECOND_PORT_ADDR 7
-
-#ifdef CONFIG_ARCH_P5040
-#define FIRST_PORT FM1_DTSEC5
-#define SECOND_PORT FM2_DTSEC5
-#else
-#define FIRST_PORT FM1_DTSEC4
-#define SECOND_PORT FM1_DTSEC5
-#endif
-
-#define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT)
-
-static void cyrus_phy_tuning(int phy)
-{
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- */
- printf("Tuning PHY @ %d\n", phy);
-
- /* sets address 0x104 or reg 260 for writing */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104);
- /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0);
- /* sets address 0x105 or reg 261 for writing */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105);
- /* writes to address 0x105 , RXD[3..0] to -0. */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
- /* sets address 0x106 or reg 261 for writing */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106);
- /* writes to address 0x106 , TXD[3..0] to -0.84ns */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
- /* force re-negotiation */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340);
-}
-#endif
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct fsl_pq_mdio_info dtsec_mdio_info;
- unsigned int i;
-
- printf("Initializing Fman\n");
-
-
- /* Register the real 1G MDIO bus */
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
-
- fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR);
- fm_info_set_mdio(FIRST_PORT,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
- fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR);
- fm_info_set_mdio(SECOND_PORT,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-
- /* Never disable DTSEC1 - it controls MDIO */
- for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- if (!IS_VALID_PORT(i))
- fm_disable_port(i);
- }
-
-#ifdef CONFIG_ARCH_P5040
- for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- if (!IS_VALID_PORT(i))
- fm_disable_port(i);
- }
-#endif
-
- cpu_eth_init(bis);
-
- cyrus_phy_tuning(FIRST_PORT_ADDR);
- cyrus_phy_tuning(SECOND_PORT_ADDR);
-#endif
-
- return pci_eth_init(bis);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Author: Adrian Cox
- * Based on corenet_ds law files.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_LBC0_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_LBC1_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-#
-# Refer docs/README.pblimage for more details about how-to configure
-# and create PBL boot image
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#PBI commands
-#Initialize CPC1 as 1MB SRAM
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-09010100 00000000
-09010104 fff0000b
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff00000
-09000d08 81000013
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Initialize eSPI controller, default configuration is slow for eSPI to
-#load data, this configuration comes from u-boot eSPI driver.
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
+++ /dev/null
-#
-# Default RCW for Cyrus P5020
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-0c540000 00000000 1e1e0000 00000000
-44808c00 ff002000 68000000 45000000
-00000000 00000000 00000000 0003000f
-a0000000 00000000 00000000 00000000
+++ /dev/null
-#
-# Default RCW for Cyrus P5040
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-90e00000 00000000 acac9800 00440000
-44808c00 ff29a000 68000000 61000000
-00000000 00000000 00000000 0003000f
-a0000000 00000000 00000000 00000000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Author: Adrian Cox
- * Based on corenet_ds tlb code
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
- * SRAM is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* Local Bus */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_64K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 11, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_4M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_CYRUS_P5020=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_CONSOLE_MUX=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_CYRUS_P5040=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_CONSOLE_MUX=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
ARCH_MPC8572 || \
ARCH_MPC8641 || \
ARCH_P4080 || \
- ARCH_P5020 || \
ARCH_P5040 || \
ARCH_LX2160A || \
ARCH_LX2162A || \
ARCH_P4080 || \
ARCH_P3041 || \
ARCH_P5040 || \
- ARCH_P5020 || \
ARCH_LS1043A || \
ARCH_LS1046A
help
obj-$(CONFIG_ARCH_P2041) += p5020.o
obj-$(CONFIG_ARCH_P3041) += p5020.o
obj-$(CONFIG_ARCH_P4080) += p4080.o
-obj-$(CONFIG_ARCH_P5020) += p5020.o
obj-$(CONFIG_ARCH_P5040) += p5040.o
obj-$(CONFIG_ARCH_T1040) += t1040.o
obj-$(CONFIG_ARCH_T1042) += t1040.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Based on corenet_ds.h
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
-#error Must call Cyrus CONFIG with a specific CPU enabled.
-#endif
-
-#define CONFIG_SDCARD
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE3
-#define CONFIG_PCIE4
-#ifdef CONFIG_ARCH_P5020
-#define CONFIG_SYS_FSL_RAID_ENGINE
-#define CONFIG_SYS_DPAA_RMAN
-#endif
-#define CONFIG_SYS_DPAA_PME
-
-/*
- * Corenet DS style board configuration file
- */
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
-#if defined(CONFIG_ARCH_P5020)
-#define CONFIG_SYS_CLK_FREQ 133000000
-#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
-#elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-#define CONFIG_SYS_MMC_MAX_DEVICE 1
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-/* test POST memory test */
-#undef CONFIG_POST
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
-#else
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
-#endif
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 1
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * Local Bus Definitions
- */
-
-#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
-#endif
-
-#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
-#else
-#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
-#endif
-
-/* Set the local bus clock 1/16 of platform clock */
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
-
-#define CONFIG_SYS_BR0_PRELIM \
-(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_BR1_PRELIM \
-(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM 0xfff00010
-#define CONFIG_SYS_OR1_PRELIM 0xfff00010
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-
-#define CONFIG_SYS_I2C_GENERIC_MAC
-#define CONFIG_SYS_I2C_MAC1_BUS 3
-#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
-#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
-#define CONFIG_SYS_I2C_MAC2_BUS 0
-#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
-#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
-
-#define CONFIG_RTC_MCP79411 1
-#define CONFIG_SYS_RTC_BUS_NUM 3
-#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-
-/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-/* Default address of microcode for the Linux Fman driver */
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_ETHPRIME "FM1@DTSEC4"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_HAS_FSL_MPH_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_EHCI_IS_TDI
- /* _VIA_CONTROL_EP */
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
-"bank_intlv=cs0_cs1;" \
-"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
-"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"fdtaddr=1e00000\0" \
-"bdev=sda3\0"
-
-#define CONFIG_HDBOOT \
-"setenv bootargs root=/dev/$bdev rw " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
-"setenv bootargs root=/dev/nfs rw " \
-"nfsroot=$serverip:$rootpath " \
-"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $ramdiskaddr $ramdiskfile;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
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