CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x100000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xD2000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x100000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xD2000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xD2000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x100000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xD2000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+ONFIG_SYS_FMAN_FW_ADDR=0x180000
+CONFIG_SYS_QE_FW_ADDR=0x200000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
+CONFIG_SYS_QE_FW_ADDR=0x124000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
+CONFIG_SYS_QE_FW_ADDR=0x130000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
+CONFIG_SYS_QE_FW_ADDR=0xEFE00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x280000
+CONFIG_SYS_QE_FW_ADDR=0x380000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x10400
+ONFIG_SYS_QE_FW_ADDR=0x124000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
+CONFIG_SYS_QE_FW_ADDR=0x130000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
+CONFIG_SYS_QE_FW_ADDR=0xEFF10000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x160000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xFFE00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x180000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+ONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x180000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x104000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0xE8020000
+CONFIG_SYS_QE_FW_ADDR=0xE8040000
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_QE=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
+CONFIG_SYS_QE_FW_ADDR=0xF00C0000
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_SYS_QE_FW_ADDR=0xf40000
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_SYS_QE_FW_ADDR=0xf40000
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
+CONFIG_SYS_QE_FW_ADDR=0x60940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
+CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x60900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x40900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+ONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
+CONFIG_SYS_FMAN_FW_ADDR=0x900000
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SYS_QE_FW_ADDR=0x60020000
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SYS_QE_FW_ADDR=0x60020000
help
This driver support the Freescale FMan Ethernet controller
+config SYS_FMAN_FW_ADDR
+ hex "FMAN Firmware Address"
+ depends on FMAN_ENET
+ default 0x0
+
+config SYS_QE_FMAN_FW_LENGTH
+ hex "FMAN QE Firmware length"
+ depends on FMAN_ENET || QE || U_QE
+ default 0x10000
+
config FTMAC100
bool "Ftmac100 Ethernet Support"
help
help
Choose this option to add support for U QUICC Engine.
+config SYS_QE_FW_ADDR
+ hex "QE Firmware Address"
+ depends on FMAN_ENET || QE || U_QE
+ default 0x0
choice
prompt "QUICC Engine FMan ethernet firmware location"
depends on FMAN_ENET || QE
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
/*
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_PCI
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
/*
#define CONFIG_SYS_DPAA_FMAN
-/* Default address of microcode for the Linux FMan driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#define CONFIG_SYS_QE_FW_ADDR 0x130000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
#ifndef __CONFIG_H
#define CONFIG_U_QE
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_QE_FW_ADDR 0x130000
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#else
-#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
-#endif
-
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_SYS_INTERLAKEN
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_SYS_INTERLAKEN
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_SYS_INTERLAKEN
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
/*
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_PCI
/* QE microcode/firmware address */
/* between the u-boot partition and env */
-#ifndef CONFIG_SYS_QE_FW_ADDR
-#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
-#endif
/*
* System IO Config
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
-#define CONFIG_SYS_QE_FW_ADDR 0x60020000
#define CONFIG_SYS_BOOTCOUNT_BE
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000
-#define CONFIG_SYS_QE_FW_ADDR 0xE8040000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
/* Qman / Bman */
/* CSU */
#define CONFIG_LAYERSCAPE_NS_ACCESS
-/* PFE */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000
-
/*SPI device */
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#endif
-#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
-
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
#define CONFIG_FSL_DEVICE_DISABLE
-
-#define CONFIG_SYS_QE_FW_ADDR 0x60940000
-
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-#define CONFIG_SYS_QE_FW_ADDR 0x60940000
-
/*
* Environment
*/
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
-#define CONFIG_SYS_QE_FW_ADDR 0x940000
-
-
-#else
-#if defined(CONFIG_SD_BOOT)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2040 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
-#else
-/* FMan fireware Pre-load address */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
-#define CONFIG_SYS_QE_FW_ADDR 0x60940000
-#endif
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#endif
-
-#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
-#else
-#ifdef CONFIG_SD_BOOT
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
-#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_FMAN_FW_ADDR (36 * (256 * 1024))
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
-#endif
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#define CONFIG_HAS_ETH2
#endif /* CONFIG_TSEC_ENET */
-#ifdef CONFIG_QE
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#endif /* CONFIG_QE */
-
/*
* Environment
*/
CONFIG_SYS_FM2_DTSEC4_PHY_ADDR
CONFIG_SYS_FM2_DTSEC_MDIO_ADDR
CONFIG_SYS_FM2_TGEC_MDIO_ADDR
-CONFIG_SYS_FMAN_FW_ADDR
CONFIG_SYS_FMAN_V3
CONFIG_SYS_FM_MURAM_SIZE
CONFIG_SYS_FORM_3U_CPCI
CONFIG_SYS_PTDPAR
CONFIG_SYS_PTV
CONFIG_SYS_PUAPAR
-CONFIG_SYS_QE_FMAN_FW_LENGTH
-CONFIG_SYS_QE_FW_ADDR
CONFIG_SYS_QMAN_CENA_BASE
CONFIG_SYS_QMAN_CENA_SIZE
CONFIG_SYS_QMAN_CINH_BASE