Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx

We already had defines for LAWAR_TRGT_IF_* that we should use
rather than creating new ones.  Also, added some missing defines for
PCIE targets.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S
index 72940b0350b294852bb137bcaf95a460d6200594..a83a0952c32fe3d733f37e380f4061f358537d3f 100644 (file)
--- a/board/cds/mpc8548cds/init.S
+++ b/board/cds/mpc8548cds/init.S
@@ -28,13 +28,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-#define LAWAR_TRGT_PCI1                0x00000000
-#define LAWAR_TRGT_PCI2                0x00100000
-#define LAWAR_TRGT_PCIE                0x00200000
-#define LAWAR_TRGT_RIO         0x00c00000
-#define LAWAR_TRGT_LBC         0x00400000
-#define LAWAR_TRGT_DDR         0x00f00000
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -232,39 +225,39 @@ law_entry:
        .long (4f-3f)/8
 3:
        .long  0
-       .long  (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+       .long  (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 
 #ifdef CFG_PCI1_MEM_PHYS
        .long   (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
        .long   (CFG_PCI1_IO_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 #endif
 
 #ifdef CFG_PCI2_MEM_PHYS
        .long   (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
        .long   (CFG_PCI2_IO_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 #endif
 
 #ifdef CFG_PCIE1_MEM_PHYS
        .long   (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
        .long   (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 #endif
 
        /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
        .long   (CFG_LBC_CACHE_BASE>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
 #ifdef CFG_RIO_MEM_PHYS
        .long   (CFG_RIO_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
 #endif
 4:
        entry_end

diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 68ccba746ba9a08c7c9ec2b6e3dbe341289698dd..084d4b80d94a63421707a1cae2a3534225e60e62 100644 (file)
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -27,13 +27,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-#define LAWAR_TRGT_PCI1                0x00000000
-#define LAWAR_TRGT_PCIE1       0x00200000
-#define LAWAR_TRGT_PCIE2       0x00100000
-#define LAWAR_TRGT_PCIE3       0x00300000
-#define LAWAR_TRGT_LBC         0x00400000
-#define LAWAR_TRGT_DDR         0x00f00000
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -212,31 +205,31 @@ law_entry:
        .long (4f-3f)/8
 3:
        .long   0
-       .long   (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+       .long   (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 
        .long   (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
        .long   (CFG_PCI1_IO_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
        .long   (CFG_LBC_CACHE_BASE>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
        .long   (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
        .long   (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
        .long   (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
        .long   (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
        /* contains both PCIE3 MEM & IO space */
        .long   (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
+       .long   LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
 4:
        entry_end

diff --git a/board/mpc8568mds/init.S b/board/mpc8568mds/init.S
index 38ba9c773d747665f5cb8ebc9bd0128f829227bc..e36036daf0de2015f2ff4cc785cf148bd4793387 100644 (file)
--- a/board/mpc8568mds/init.S
+++ b/board/mpc8568mds/init.S
@@ -28,12 +28,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-#define LAWAR_TRGT_PCI1         0x00000000
-#define LAWAR_TRGT_PCIE1       0x00200000
-#define LAWAR_TRGT_RIO          0x00c00000
-#define LAWAR_TRGT_LBC          0x00400000
-#define LAWAR_TRGT_DDR          0x00f00000
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -216,27 +210,26 @@ tlb1_entry:
  */
 
 #define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 
 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
 #define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
+#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
 #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 /* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
 #define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 
        .section .bootpg, "ax"
        .globl  law_entry

diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index b3cfa9b37268dde73f6a5cd70b04e327e01f63c7..3d403327e0ef509434d43d34b54ff41948918404 100644 (file)
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -413,7 +413,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define LAWAR_TRGT_IF_PCI1     0x00000000
 #define LAWAR_TRGT_IF_PCIX     0x00000000
 #define LAWAR_TRGT_IF_PCI2     0x00100000
-#define LAWAR_TRGT_IF_PEX      0x00200000
+#define LAWAR_TRGT_IF_PCIE1    0x00200000
+#define LAWAR_TRGT_IF_PCIE2    0x00100000
+#define LAWAR_TRGT_IF_PCIE3    0x00300000
 #define LAWAR_TRGT_IF_LBC      0x00400000
 #define LAWAR_TRGT_IF_CCSR     0x00800000
 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000