/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2020 Intel Corporation <www.intel.com>
*
*/
/*
* Offset for HW handoff from Quartus tools
*/
-#define SOC64_HANDOFF_BASE 0xFFE3F000
-#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
-#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0)
-#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
-#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0)
-#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580)
-#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+/* HPS handoff */
#define SOC64_HANDOFF_MAGIC_MUX 0x504D5558
#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
+
#define SOC64_HANDOFF_OFFSET_LENGTH 0x4
#define SOC64_HANDOFF_OFFSET_DATA 0x10
+#define SOC64_HANDOFF_SIZE 4096
+
+#define SOC64_HANDOFF_BASE 0xFFE3F000
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
+#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0)
+#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
+#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0)
+#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580)
#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
#endif
-#define SOC64_HANDOFF_SIZE 4096
-
#endif /* _HANDOFF_SOC64_H_ */