imx9: add more PLL settings

Add more PLL settings for A55 and Display

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 51aa259aa05748691cee8927c68ec87d7289b1fc..7d3a4c01333f3dd11b66dd396b840c1cec893556 100644 (file)
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -26,6 +26,7 @@ static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR;
 static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
        INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */
        INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */
+       INT_PLL_RATE(1500000000U, 1, 125, 2), /* 1.5Ghz */
        INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
        INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
        INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
@@ -35,8 +36,11 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
        FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
        FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
        FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
+       FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
+       FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
        FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
        FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
+       FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
 };
 
 /* return in khz */