arm: mx6: cm_fx6: add nand support

Add NAND support for Compulab CM-FX6 CoM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index b5895816cb010ee49d88ff33c9f29dc69422485d..17c3ee5aef48213be7a4860d0a2c4a8b45c171f2 100644 (file)
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -10,11 +10,46 @@
 
 #include <common.h>
 #include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/io.h>
 #include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+       IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_gpmi_nand(void)
+{
+       SETUP_IOMUX_PADS(nand_pads);
+       /* Enable clock roots */
+       enable_usdhc_clk(1, 3);
+       enable_usdhc_clk(1, 4);
+
+       setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
+                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
+                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
+}
+#else
+static void cm_fx6_setup_gpmi_nand(void) {}
+#endif
+
 #ifdef CONFIG_FSL_ESDHC
 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
        {USDHC1_BASE_ADDR},
@@ -47,6 +82,8 @@ int board_mmc_init(bd_t *bis)
 int board_init(void)
 {
        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+       cm_fx6_setup_gpmi_nand();
+
        return 0;
 }
 

diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
index a3abc7b3f32f9c5084e683a5f8f3e7621a7dc3ed..3948ba23ae9e4267bfaa7b3d6f59aeb5b894c1ac 100644 (file)
--- a/board/compulab/cm_fx6/spl.c
+++ b/board/compulab/cm_fx6/spl.c
@@ -15,6 +15,7 @@
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <fsl_esdhc.h>
 #include "common.h"
@@ -309,7 +310,17 @@ static void cm_fx6_setup_ecspi(void) { }
 
 void board_init_f(ulong dummy)
 {
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
        gd = &gdata;
+       /*
+        * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
+        * initializes DMA very early (before all board code), so the only
+        * opportunity we have to initialize APBHDMA clocks is in SPL.
+        */
+       setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+       enable_usdhc_clk(1, 2);
+
        arch_cpu_init();
        timer_init();
        cm_fx6_setup_ecspi();

diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 15c55beec3c12c5955692766a598691c8158daea..4c1bcb90d2913478c2defa135ebca4e0806b0599 100644 (file)
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -130,6 +130,20 @@
        "mmcboot=echo Booting from mmc ...; " \
                "run mmcargs; " \
                "run doboot\0" \
+       "nandroot=/dev/mtdblock4 rw\0" \
+       "nandrootfstype=ubifs\0" \
+       "nandargs=setenv bootargs console=${console} " \
+               "root=${nandroot} " \
+               "rootfstype=${nandrootfstype} " \
+               "${video}\0" \
+       "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
+       "nandboot=echo Booting from nand ...; " \
+               "run nandargs; " \
+               "nand read ${loadaddr} 0 780000; " \
+               "if ${loadfdt}; then " \
+                       "run nandloadfdt;" \
+               "fi; " \
+               "run doboot\0" \
        "boot=mmc dev ${mmcdev}; " \
                "if mmc rescan; then " \
                        "if run loadmmcbootscript; then " \
@@ -142,7 +156,8 @@
                                        "run mmcboot;" \
                                "fi;" \
                        "fi;" \
-               "fi;\0"
+               "fi;" \
+               "run nandboot\0"
 
 #define CONFIG_BOOTCOMMAND \
        "run setboottypem; run boot"
@@ -160,6 +175,20 @@
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_WINBOND
 
+/* NAND */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_MAX_CHIPS      1
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* APBH DMA is required for NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
 /* GPIO */
 #define CONFIG_MXC_GPIO