Add Elpida Memory Configuration to mpc5121ads Boards

Signed-off-by: Martha M Stan <mmarx@silicontkx.com>
Minor coding style cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>

diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 8defb001a38f40f710af33f73013f39af9c72667..3323d66a3c3f7a64d1ea7e1ff3f7306110462ad0 100644 (file)
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -31,6 +31,7 @@
 #ifdef CONFIG_MISC_INIT_R
 #include <i2c.h>
 #endif
+#include <net.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -133,11 +134,105 @@ int board_early_init_f(void)
        return 0;
 }
 
+int is_micron(void){
+
+       ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
+       uchar macaddr[6];
+       u32 brddate, macchk, ismicron;
+
+       /*
+        * MAC address has serial number with date of manufacture
+        * Boards made before Nov-08 #1180 use Micron memory;
+        * 001e59 is the STx vendor #
+        * Default is Elpida since it works for both but is slightly slower
+        */
+       ismicron = 0;
+       if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
+               brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
+               macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
+               debug("brddate = %d\n\t", brddate);
+
+               if (macchk == 0x001e59 && brddate <= 8111180)
+                       ismicron = 1;
+       } else if (brd_rev < 0x400) {
+               ismicron = 1;
+       }
+       debug("Using %s Memory settings\n\t",
+               ismicron ? "Micron" : "Elpida");
+       return(ismicron);
+}
+
 phys_size_t initdram(int board_type)
 {
        u32 msize = 0;
-
-       msize = fixed_sdram(NULL, NULL, 0);
+       /*
+        * Elpida MDDRC and initialization settings are an alternative
+        * to the Default Micron ones for all but the earliest Rev 4 boards
+        */
+       u32 elpida_mddrc_config[4] = {
+               CONFIG_SYS_MDDRC_TIME_CFG0,
+               CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
+               CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA
+               CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+       };
+
+       u32 elpida_init_sequence[] = {
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_PCHG_ALL,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_RFSH,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_RFSH,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_EM2,
+               CONFIG_SYS_DDRCMD_EM3,
+               CONFIG_SYS_DDRCMD_EN_DLL,
+               CONFIG_SYS_ELPIDA_RES_DLL,
+               CONFIG_SYS_DDRCMD_PCHG_ALL,
+               CONFIG_SYS_DDRCMD_RFSH,
+               CONFIG_SYS_DDRCMD_RFSH,
+               CONFIG_SYS_DDRCMD_RFSH,
+               CONFIG_SYS_ELPIDA_INIT_DEV_OP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+               CONFIG_SYS_ELPIDA_OCD_EXIT,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP,
+               CONFIG_SYS_DDRCMD_NOP
+       };
+
+       if (is_micron()) {
+               msize = fixed_sdram(NULL, NULL, 0);
+       } else {
+               msize = fixed_sdram(elpida_mddrc_config,
+                               elpida_init_sequence,
+                               sizeof(elpida_init_sequence)/sizeof(u32));
+       }
 
        return msize;
 }

diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 0c871c919519a76349c486abc4b1f52907294077..ebc518c03c16efa279906fe43e68de91f0c19d97 100644 (file)
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -141,14 +141,45 @@
 #endif
 #define CONFIG_SYS_MDDRC_TIME_CFG0     0x06183D2E
 
+#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA                0xEA802B00
+#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA      0x690e1189
+#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA      0x35310864
+
 #define CONFIG_SYS_DDRCMD_NOP          0x01380000
 #define CONFIG_SYS_DDRCMD_PCHG_ALL     0x01100400
 #define CONFIG_SYS_DDRCMD_EM2          0x01020000
 #define CONFIG_SYS_DDRCMD_EM3          0x01030000
 #define CONFIG_SYS_DDRCMD_EN_DLL       0x01010000
 #define CONFIG_SYS_DDRCMD_RFSH         0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP  0x01000432
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT  0x01010780
+
+#define DDRCMD_EMR_OCD(pr, ohm) ( \
+       (1 << 24)          | /* MDDRC Command Request   */ \
+       (1 << 16)          | /* MODE Reg BA[2:0]        */ \
+       (0 << 12)          | /* Outputs 0=Enabled       */ \
+       (0 << 11)          | /* RDQS                    */ \
+       (1 << 10)          | /* DQS#                    */ \
+       (pr <<  7)         | /* OCD prog 7=deflt,0=exit */ \
+                   /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
+       ((ohm & 0x2) <<  5)| /* Rtt1                    */ \
+       (0 <<  3)          | /* additive posted CAS#    */ \
+       ((ohm & 0x1) <<  2)| /* Rtt0                    */ \
+       (0 <<  0)          | /* Output Drive Strength   */ \
+       (0 <<  0))           /* DLL Enable 0=Normal     */
+
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT  DDRCMD_EMR_OCD(7, 0)
+#define CONFIG_SYS_ELPIDA_OCD_EXIT     DDRCMD_EMR_OCD(0, 0)
+
+#define DDRCMD_MODE_REG(cas, wr) ( \
+       (1 << 24)    | /* MDDRC Command Request                 */ \
+       (0 << 16)    | /* MODE Reg BA[2:0]                      */ \
+       ((wr-1) << 9)| /* Write Recovery                        */ \
+       (cas << 4)   | /* CAS                                   */ \
+       (0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved */ \
+       (2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8       */
+
+#define CONFIG_SYS_MICRON_INIT_DEV_OP  DDRCMD_MODE_REG(3, 3)
+#define CONFIG_SYS_ELPIDA_INIT_DEV_OP  DDRCMD_MODE_REG(4, 4)
+#define CONFIG_SYS_ELPIDA_RES_DLL      (DDRCMD_MODE_REG(4, 4) | (1 << 8))
 
 /* DDR Priority Manager Configuration */
 #define CONFIG_SYS_MDDRCGRP_PM_CFG1    0x00077777