]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
nios2: convert altera timer to driver model
authorThomas Chou <thomas@wytron.com.tw>
Thu, 22 Oct 2015 14:28:53 +0000 (22:28 +0800)
committerThomas Chou <thomas@wytron.com.tw>
Thu, 22 Oct 2015 23:37:03 +0000 (07:37 +0800)
Convert altera timer to driver model.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
arch/nios2/cpu/Makefile
arch/nios2/cpu/timer.c [deleted file]
common/board_f.c
configs/nios2-generic_defconfig
doc/device-tree-bindings/timer/altera_timer.txt [new file with mode: 0644]
drivers/timer/Kconfig
drivers/timer/Makefile
drivers/timer/altera_timer.c [new file with mode: 0644]
include/configs/nios2-generic.h

index c85e26169d49033e30a0f714940e36935211301e..3fe7847160d5afbcd752415eb3c2657e20312eb9 100644 (file)
@@ -7,5 +7,5 @@
 
 extra-y        = start.o
 obj-y  = exceptions.o
-obj-y  += cpu.o interrupts.o sysid.o timer.o traps.o
+obj-y  += cpu.o interrupts.o sysid.o traps.o
 obj-y  += fdt.o
diff --git a/arch/nios2/cpu/timer.c b/arch/nios2/cpu/timer.c
deleted file mode 100644 (file)
index b8aa9dd..0000000
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/nios2.h>
-#include <asm/types.h>
-#include <asm/io.h>
-
-struct nios_timer {
-       u32     status;         /* Timer status reg */
-       u32     control;        /* Timer control reg */
-       u32     periodl;        /* Timeout period low */
-       u32     periodh;        /* Timeout period high */
-       u32     snapl;          /* Snapshot low */
-       u32     snaph;          /* Snapshot high */
-};
-
-/* status register */
-#define NIOS_TIMER_TO          (1 << 0)        /* Timeout */
-#define NIOS_TIMER_RUN         (1 << 1)        /* Timer running */
-
-/* control register */
-#define NIOS_TIMER_ITO         (1 << 0)        /* Timeout interrupt enable */
-#define NIOS_TIMER_CONT                (1 << 1)        /* Continuous mode */
-#define NIOS_TIMER_START       (1 << 2)        /* Start timer */
-#define NIOS_TIMER_STOP                (1 << 3)        /* Stop timer */
-
-/*************************************************************************/
-unsigned long notrace timer_read_counter(void)
-{
-       struct nios_timer *tmr = (struct nios_timer *)CONFIG_SYS_TIMER_BASE;
-       u32 val;
-
-       /* Trigger update */
-       writel(0x0, &tmr->snapl);
-
-       /* Read timer value */
-       val = readl(&tmr->snapl) & 0xffff;
-       val |= (readl(&tmr->snaph) & 0xffff) << 16;
-
-       return ~val;
-}
-
-int timer_init(void)
-{
-       struct nios_timer *tmr = (struct nios_timer *)CONFIG_SYS_TIMER_BASE;
-
-       writel(0, &tmr->status);
-       writel(0, &tmr->control);
-       writel(NIOS_TIMER_STOP, &tmr->control);
-
-       writel(0xffff, &tmr->periodl);
-       writel(0xffff, &tmr->periodh);
-
-       writel(NIOS_TIMER_CONT | NIOS_TIMER_START, &tmr->control);
-
-       return 0;
-}
index 8bb8ded50e41bf25e43e385ac64f17d04b8e0626..613332e1dc3f6c49058aaa7610dc7001d9b7ce85 100644 (file)
@@ -795,8 +795,7 @@ static init_fnc_t init_sequence_f[] = {
        init_timebase,
 #endif
 #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
-               defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
-               defined(CONFIG_NIOS2)
+               defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32)
        timer_init,             /* initialize timer */
 #endif
 #ifdef CONFIG_SYS_ALLOC_DPRAM
index 707ee3363fbd9ca41e3a690710013720e193ec4e..505a2cf8be388e7aa5b5fb032cf150013c7ea5cf 100644 (file)
@@ -18,3 +18,5 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ALTERA_PIO=y
 CONFIG_ALTERA_JTAG_UART=y
 CONFIG_ALTERA_JTAG_UART_BYPASS=y
+CONFIG_TIMER=y
+CONFIG_ALTERA_TIMER=y
diff --git a/doc/device-tree-bindings/timer/altera_timer.txt b/doc/device-tree-bindings/timer/altera_timer.txt
new file mode 100644 (file)
index 0000000..904a584
--- /dev/null
@@ -0,0 +1,19 @@
+Altera Timer
+
+Required properties:
+
+- compatible : should be "altr,timer-1.0"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-parent: phandle of the interrupt controller
+- interrupts : Should contain the timer interrupt number
+- clock-frequency : The frequency of the clock that drives the counter, in Hz.
+
+Example:
+
+timer {
+       compatible = "altr,timer-1.0";
+       reg = <0x00400000 0x00000020>;
+       interrupt-parent = <&cpu>;
+       interrupts = <11>;
+       clock-frequency = <125000000>;
+};
index 8e8d6006b01a2dbf3d056eea9a71b68aeaef76c6..97c41280052eab5569f4af8d0ee6d02a40d05c07 100644 (file)
@@ -9,4 +9,11 @@ config TIMER
          will be used. The timer is usually a 32 bits free-running up
          counter. There may be no real tick, and no timer interrupt.
 
+config ALTERA_TIMER
+       bool "Altera Timer support"
+       depends on TIMER
+       help
+         Select this to enable an timer for Altera devices. Please find
+         details on the "Embedded Peripherals IP User Guide" of Altera.
+
 endmenu
index afb0009111e9d70ba764384ecc8e4adb5284d9dc..ae66c07d0e41ebfc6abb5dcb180eb2a928e2c472 100644 (file)
@@ -5,3 +5,4 @@
 #
 
 obj-$(CONFIG_TIMER)            += timer-uclass.o
+obj-$(CONFIG_ALTERA_TIMER)     += altera_timer.o
diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c
new file mode 100644 (file)
index 0000000..2ef9ad6
--- /dev/null
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <timer.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct altera_timer_regs {
+       u32     status;         /* Timer status reg */
+       u32     control;        /* Timer control reg */
+       u32     periodl;        /* Timeout period low */
+       u32     periodh;        /* Timeout period high */
+       u32     snapl;          /* Snapshot low */
+       u32     snaph;          /* Snapshot high */
+};
+
+struct altera_timer_platdata {
+       struct altera_timer_regs *regs;
+       unsigned long clock_rate;
+};
+
+/* control register */
+#define ALTERA_TIMER_CONT      (1 << 1)        /* Continuous mode */
+#define ALTERA_TIMER_START     (1 << 2)        /* Start timer */
+#define ALTERA_TIMER_STOP      (1 << 3)        /* Stop timer */
+
+static int altera_timer_get_count(struct udevice *dev, unsigned long *count)
+{
+       struct altera_timer_platdata *plat = dev->platdata;
+       struct altera_timer_regs *const regs = plat->regs;
+       u32 val;
+
+       /* Trigger update */
+       writel(0x0, &regs->snapl);
+
+       /* Read timer value */
+       val = readl(&regs->snapl) & 0xffff;
+       val |= (readl(&regs->snaph) & 0xffff) << 16;
+       *count = ~val;
+
+       return 0;
+}
+
+static int altera_timer_probe(struct udevice *dev)
+{
+       struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+       struct altera_timer_platdata *plat = dev->platdata;
+       struct altera_timer_regs *const regs = plat->regs;
+
+       uc_priv->clock_rate = plat->clock_rate;
+
+       writel(0, &regs->status);
+       writel(0, &regs->control);
+       writel(ALTERA_TIMER_STOP, &regs->control);
+
+       writel(0xffff, &regs->periodl);
+       writel(0xffff, &regs->periodh);
+       writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, &regs->control);
+
+       return 0;
+}
+
+static int altera_timer_ofdata_to_platdata(struct udevice *dev)
+{
+       struct altera_timer_platdata *plat = dev_get_platdata(dev);
+
+       plat->regs = ioremap(dev_get_addr(dev),
+               sizeof(struct altera_timer_regs));
+       plat->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+               "clock-frequency", 0);
+
+       return 0;
+}
+
+static const struct timer_ops altera_timer_ops = {
+       .get_count = altera_timer_get_count,
+};
+
+static const struct udevice_id altera_timer_ids[] = {
+       { .compatible = "altr,timer-1.0", },
+       { }
+};
+
+U_BOOT_DRIVER(altera_timer) = {
+       .name   = "altera_timer",
+       .id     = UCLASS_TIMER,
+       .of_match = altera_timer_ids,
+       .ofdata_to_platdata = altera_timer_ofdata_to_platdata,
+       .platdata_auto_alloc_size = sizeof(struct altera_timer_platdata),
+       .probe = altera_timer_probe,
+       .ops    = &altera_timer_ops,
+       .flags = DM_FLAG_PRE_RELOC,
+};
index 62f7db963dd9f09913ff7f8af7f9460a79ec898b..c65b3b3e6d0d09157f2a7bcac7aeeee4a78ff45b 100644 (file)
 #define CONFIG_BAUDRATE                        115200
 #define CONFIG_SYS_CONSOLE_INFO_QUIET  /* Suppress console info */
 
-/*
- * TIMER
- */
-#define CONFIG_SYS_TIMER_RATE          CONFIG_SYS_TIMER_FREQ
-
 /*
  * BOOTP options
  */