x86: qemu: setup PM IO base for ACPI in southbridge

Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board)

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index 4f9862194a97e094b9cabee0439828453a1b4e28..6808c9a6b9a262b5ce67b2708e396902505d8b0c 100644 (file)
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -17,4 +17,11 @@ config SYS_CAR_SIZE
        hex
        default 0x10000
 
+config ACPI_PM1_BASE
+       hex
+       default 0xe400
+       help
+         ACPI Power Managment 1 (PM1) i/o-mapped base address.
+         This device is defined in ACPI specification, with 16 bytes in size.
+
 endif

diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 5a7b92944a21501edd10b99824cb2eab337e0da1..f8af566deae80d714e2516aa04c370b6eed20c9a 100644 (file)
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -15,6 +15,31 @@
 
 static bool i440fx;
 
+static void enable_pm_piix(void)
+{
+       u8 en;
+       u16 cmd;
+
+       /* Set the PM I/O base */
+       x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+
+       /* Enable access to the PM I/O space */
+       cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND);
+       cmd |= PCI_COMMAND_IO;
+       x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
+
+       /* PM I/O Space Enable (PMIOSE) */
+       en = x86_pci_read_config8(PIIX_PM, PMREGMISC);
+       en |= PMIOSE;
+       x86_pci_write_config8(PIIX_PM, PMREGMISC, en);
+}
+
+static void enable_pm_ich9(void)
+{
+       /* Set the PM I/O base */
+       x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+}
+
 static void qemu_chipset_init(void)
 {
        u16 device, xbcs;
@@ -53,10 +78,14 @@ static void qemu_chipset_init(void)
                xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
                xbcs |= APIC_EN;
                x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
+
+               enable_pm_piix();
        } else {
                /* Configure PCIe ECAM base address */
                x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
                                       CONFIG_PCIE_ECAM_BASE | BAR_EN);
+
+               enable_pm_ich9();
        }
 
        qemu_fwcfg_init();

diff --git a/arch/x86/include/asm/arch-qemu/device.h b/arch/x86/include/asm/arch-qemu/device.h
index 75a435e67b9ff294e33035b0cfaf83b811ef40f2..38ab798994f00e36d26d4e6e8148810eb8be0b42 100644 (file)
--- a/arch/x86/include/asm/arch-qemu/device.h
+++ b/arch/x86/include/asm/arch-qemu/device.h
@@ -13,6 +13,8 @@
 #define PIIX_ISA       PCI_BDF(0, 1, 0)
 #define PIIX_IDE       PCI_BDF(0, 1, 1)
 #define PIIX_USB       PCI_BDF(0, 1, 2)
+#define PIIX_PM        PCI_BDF(0, 1, 3)
+#define ICH9_PM        PCI_BDF(0, 0x1f, 0)
 #define I440FX_VGA     PCI_BDF(0, 2, 0)
 
 #define QEMU_Q35       PCI_BDF(0, 0, 0)

diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h
index b67d3428ee69711f5e469aa70ebd13146e073fa7..a85eee8ec6d13bd6078b45a6c74cf9bcab50026b 100644 (file)
--- a/arch/x86/include/asm/arch-qemu/qemu.h
+++ b/arch/x86/include/asm/arch-qemu/qemu.h
@@ -33,4 +33,9 @@
 #define LOW_RAM_ADDR           0x34
 #define HIGH_RAM_ADDR          0x35
 
+/* PM registers */
+#define PMBA           0x40
+#define PMREGMISC      0x80
+#define PMIOSE         (1 << 0)
+
 #endif /* _ARCH_QEMU_H_ */