]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
Convert CONFIG_BTB to Kconfig
authorTom Rini <trini@konsulko.com>
Wed, 23 Feb 2022 17:28:15 +0000 (12:28 -0500)
committerTom Rini <trini@konsulko.com>
Thu, 3 Mar 2022 21:51:19 +0000 (16:51 -0500)
This converts the following to Kconfig:
   CONFIG_BTB

Signed-off-by: Tom Rini <trini@konsulko.com>
13 files changed:
arch/powerpc/cpu/mpc85xx/Kconfig
include/configs/MPC8548CDS.h
include/configs/P1010RDB.h
include/configs/P2041RDB.h
include/configs/T102xRDB.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240RDB.h
include/configs/corenet_ds.h
include/configs/kmcent2.h
include/configs/p1_p2_rdb_pc.h
include/configs/socrates.h

index c308447d493a5954bbe9a04a0f06b37c6f86e1d1..a978eea1617a211078842d313dc679a8cf752150 100644 (file)
@@ -317,6 +317,7 @@ config ARCH_MPC8540
 
 config ARCH_MPC8544
        bool
+       select BTB
        select FSL_LAW
        select SYS_CACHE_SHIFT_5
        select SYS_FSL_ERRATUM_A005125
@@ -330,6 +331,7 @@ config ARCH_MPC8544
 
 config ARCH_MPC8548
        bool
+       select BTB
        select FSL_LAW
        select SYS_FSL_ERRATUM_A005125
        select SYS_FSL_ERRATUM_NMG_DDR120
@@ -352,6 +354,7 @@ config ARCH_MPC8560
 
 config ARCH_P1010
        bool
+       select BTB
        select FSL_LAW
        select SYS_CACHE_SHIFT_5
        select SYS_HAS_SERDES
@@ -400,6 +403,7 @@ config ARCH_P1011
 
 config ARCH_P1020
        bool
+       select BTB
        select FSL_LAW
        select SYS_CACHE_SHIFT_5
        select SYS_FSL_ERRATUM_A004508
@@ -496,6 +500,7 @@ config ARCH_P1025
 
 config ARCH_P2020
        bool
+       select BTB
        select FSL_LAW
        select SYS_CACHE_SHIFT_5
        select SYS_FSL_ERRATUM_A004477
@@ -772,6 +777,9 @@ config MPC85XX_HAVE_RESET_VECTOR
        bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
        depends on MPC85xx
 
+config BTB
+       bool "toggle branch predition"
+
 config BOOKE
        bool
        default y
@@ -784,12 +792,14 @@ config E500
 
 config E500MC
        bool
+       select BTB
        imply CMD_PCI
        help
                Enble PowerPC E500MC core
 
 config E6500
        bool
+       select BTB
        help
                Enable PowerPC E6500 core
 
index e16d870a5e66d5d1175d83712fa433f7770e4a66..b5430c950d036a5d0e48206a740c55393019ef6b 100644 (file)
@@ -30,7 +30,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache */
-#define CONFIG_BTB                     /* toggle branch predition */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
index 106d1e6a4b7e8470fb330ddd5e25c31e34068485..827edf484b764d6efb49cfc8b8b5953c518202ab 100644 (file)
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache */
-#define CONFIG_BTB                     /* toggle branch predition */
 
 
 #define CONFIG_ENABLE_36BIT_PHYS
index e6d5321070bfe1399e92a65b99eb90be51758db8..027f1479319d8291d8b35ea72e0c00a8a619c0e5 100644 (file)
@@ -58,7 +58,6 @@
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
index d24cfce8b3b9a0c700ce38f32a1c28dd99c83417..2fe53bf6be9f2d83f7576f9b45d6f35fc0e088aa 100644 (file)
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
index 9433f14227bb40d29fd112bf1605928d77cff92b..2c4ede960ec10ea3254285a8a03b719b135fbdc4 100644 (file)
@@ -98,7 +98,6 @@
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
index a41f9f0d9b832c3499e07e6dee5a9d3405b52190..3fcab6a0213c330b468f173a20f36aface7a508c 100644 (file)
@@ -88,7 +88,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB             /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
index 7165ba08283329ad6b12f037f2e1bca72bf76b3b..8a725cd1f78fba0c13ab6debd33dba1fdbce21ac 100644 (file)
@@ -83,7 +83,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB             /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
index daccd816c1040ea62b471f4dff99fa54a369547c..441ff18441a6b5e9fdd3bbf885660683d4408cf0 100644 (file)
@@ -65,7 +65,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB                     /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
index bd264122da76fd39140c059cbe2cf2b786c9c9e8..79c90a7addb8e09876257842ce4a3c7618b6ff1d 100644 (file)
@@ -59,7 +59,6 @@
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
index ca0cb31c296405560f871adfa333050e12fdf274..52a5ff9382ed91a016fed53f0b3027bfc4c50089 100644 (file)
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
index 92008cd38e49326041955ed009d714b0dd7ecc87..549adf04b62d5d6e9e60791a809d22bbff1b408c 100644 (file)
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE
-#define CONFIG_BTB
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
index a51a162ee044a0b4859e04904c6dc5df1221fe9b..4eb19b0e3e3fcac820dca36425c2913af73ee96e 100644 (file)
@@ -42,7 +42,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache              */
-#define CONFIG_BTB                     /* toggle branch predition      */
 
 #define CONFIG_SYS_INIT_DBCR DBCR_IDM          /* Enable Debug Exceptions      */