]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm: dts: mt7622: add USB nodes
authorFrank Wunderlich <frank-w@public-files.de>
Thu, 20 Aug 2020 14:37:57 +0000 (16:37 +0200)
committerTom Rini <trini@konsulko.com>
Mon, 24 Aug 2020 18:11:31 +0000 (14:11 -0400)
Add DTS nodes for MT7622/BPI-R64

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
arch/arm/dts/mt7622-bananapi-bpi-r64.dts
arch/arm/dts/mt7622-rfb.dts
arch/arm/dts/mt7622.dtsi

index 51287cea3ac8ebbe2e357adf156c7cd8cefd916f..4f2f04851d10a5d448a0ec1280d48e38bb681f4d 100644 (file)
                output-low;
        };
 };
+
+&ssusb {
+       status = "okay";
+};
+
+&u3phy {
+       status = "okay";
+};
index 317fc78abdac663e05d790ad3e84dc0547df274a..ef7d0f0270e9c2d13f87df64c6fe9d29cb31bea4 100644 (file)
                full-duplex;
        };
 };
+
+&ssusb {
+       status = "okay";
+};
+
+&u3phy {
+       status = "okay";
+};
index c43ad6570299035073d422d5c1dc8ccbcfc790fc..d888545809199d1e7e76e078cb43e2fc37c8743d 100644 (file)
                status = "disabled";
        };
 
+       ssusbsys: ssusbsys@1a000000 {
+               compatible = "mediatek,mt7622-ssusbsys",
+                            "syscon";
+               reg = <0x1a000000 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
        pciesys: pciesys@1a100800 {
                compatible = "mediatek,mt7622-pciesys", "syscon";
                reg = <0x1a100800 0x1000>;
                };
        };
 
+       ssusb: usb@1a0c0000 {
+               compatible = "mediatek,mt7622-xhci",
+                            "mediatek,mtk-xhci";
+               reg = <0x1a0c0000 0x01000>,
+                     <0x1a0c4700 0x0100>;
+               reg-names = "mac", "ippc";
+               interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+               power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
+               clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+                        <&ssusbsys CLK_SSUSB_REF_EN>,
+                        <&ssusbsys CLK_SSUSB_MCU_EN>,
+                        <&ssusbsys CLK_SSUSB_DMA_EN>;
+               clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+               phys = <&u2port0 PHY_TYPE_USB2>,
+                      <&u3port0 PHY_TYPE_USB3>,
+                      <&u2port1 PHY_TYPE_USB2>;
+               status = "disabled";
+       };
+
+       u3phy: usb-phy@1a0c4000 {
+               compatible = "mediatek,mt7622-u3phy",
+                            "mediatek,generic-tphy-v1";
+               reg = <0x1a0c4000 0x700>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               status = "disabled";
+
+               u2port0: usb-phy@1a0c4800 {
+                       reg = <0x1a0c4800 0x0100>;
+                       #phy-cells = <1>;
+                       clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+                       clock-names = "ref";
+               };
+
+               u3port0: usb-phy@1a0c4900 {
+                       reg = <0x1a0c4900 0x0700>;
+                       #phy-cells = <1>;
+               };
+
+               u2port1: usb-phy@1a0c5000 {
+                       reg = <0x1a0c5000 0x0100>;
+                       #phy-cells = <1>;
+                       clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
+                       clock-names = "ref";
+               };
+       };
+
        ethsys: syscon@1b000000 {
                compatible = "mediatek,mt7622-ethsys", "syscon";
                reg = <0x1b000000 0x1000>;