ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bit

Now that bit 29 is the USB PHY reset bit, update the Kilauea port
to remove the USB PHY reset after powerup. The CPLD will keep the
USB PHY in reset (active low) until the bit is set to 1 in
board_early_init_f().

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 2ee896abd9669c73fae73df27a6a6c18b71166ee..37ef06ef2a77648fd26c482ff2873afd9819a7f7 100644 (file)
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -192,13 +192,6 @@ int board_early_init_f (void)
         */
        mtsdr(SDR0_SRST, 0);
 
-       /*
-        * Configure FPGA register with PCIe reset
-        */
-       out_be32((void *)CFG_FPGA_BASE, 0xff570cc0);    /* assert PCIe reset */
-       mdelay(50);
-       out_be32((void *)CFG_FPGA_BASE, 0xff570cc3);    /* deassert PCIe reset */
-
        /* Configure 405EX for NAND usage */
        val = SDR0_CUST0_MUX_NDFC_SEL |
                SDR0_CUST0_NDFC_ENABLE |
@@ -214,6 +207,13 @@ int board_early_init_f (void)
        val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
        mtsdr(SDR0_PFC1, val);
 
+       /*
+        * Configure FPGA register with PCIe reset
+        */
+       out_be32((void *)CFG_FPGA_BASE, 0xff570cc4);    /* assert PCIe reset */
+       mdelay(50);
+       out_be32((void *)CFG_FPGA_BASE, 0xff570cc7);    /* deassert PCIe reset */
+
        return 0;
 }