config SYS_FSL_QSPI_SKIP_CLKSEL
bool "Skip setting QSPI clock during SoC init"
- default 0
help
To improve startup times when booting from QSPI flash, the QSPI
frequency can be set very early in the boot process. If this option
config SYS_FSL_BOOTROM_BASE
hex
depends on FSL_LSCH2
- default 0
+ default 0x0
config SYS_FSL_BOOTROM_SIZE
hex
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
depends on IMX8_ROMAPI || SPL_BOOTROM_SUPPORT
- default 0
+ default 0x0
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
config BOOTAUX_RESERVED_MEM_BASE
hex "i.MX auxiliary core dram memory base"
- default 0
+ default 0x0
config BOOTAUX_RESERVED_MEM_SIZE
hex "i.MX auxiliary core dram memory size"
- default 0
+ default 0x0
choice
prompt "i.MX8 board select"
config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
- default 0
+ default 0x0
help
SPL may need reserve memory for firmware loaded by SPL, whose load
address is in IRAM and may overlay with SPL text area if not
config DRAM_TPR3
hex "sunxi dram tpr3 value"
- default 0
+ default 0x0
---help---
Set the dram controller tpr3 parameter. This parameter configures
the delay on the command lane and also phase shifts, which are
config DRAM_DQS_GATING_DELAY
hex "sunxi dram dqs_gating_delay value"
- default 0
+ default 0x0
---help---
Set the dram controller dqs_gating_delay parmeter. Each byte
encodes the DQS gating delay for each byte lane. The delay
config SYS_SYPCR
hex "SYPCR register" if !WDT_MPC8xxx
- default 0
+ default 0x0
help
System Protection Control (11-9)
config BOOTSTAGE_STASH_ADDR
hex "Address to stash boot timing information"
- default 0
+ default 0x0
help
Provide an address which will not be overwritten by the OS when it
starts, so that it can read this information when ready.
config CMD_SPL_NAND_OFS
hex "Offset of OS args or dtb for Falcon-mode NAND boot"
depends on CMD_SPL && (TPL_NAND_SUPPORT || SPL_NAND_SUPPORT)
- default 0
+ default 0x0
help
This provides the offset of the command line arguments for Linux
when booting from NAND in Falcon mode. See doc/README.falcon
config CMD_SPL_NOR_OFS
hex "Offset of OS args or dtb for Falcon-mode NOR boot"
depends on CMD_SPL && SPL_NOR_SUPPORT
- default 0
+ default 0x0
help
This provides the offset of the command line arguments or dtb for
Linux when booting from NOR in Falcon mode.
config DEFAULT_SPI_MODE
hex "default spi mode used by sspi command (see include/spi.h)"
depends on CMD_SPI
- default 0
+ default 0x0
config CMD_TEMPERATURE
bool "temperature - display the temperature from thermal sensors"
depends on BOOTP_PXE
default 0x16 if ARM64
default 0x15 if ARM
- default 0 if X86
+ default 0x0 if X86
config BOOTP_VCI_STRING
string
config BLOBLIST_SIZE_RELOC
hex "Size of bloblist after relocation"
default BLOBLIST_SIZE if BLOBLIST_FIXED || BLOBLIST_ALLOC
- default 0 if BLOBLIST_PASSAGE
+ default 0x0 if BLOBLIST_PASSAGE
help
Sets the size of the bloblist in bytes after relocation. Since U-Boot
has a lot more memory available then, it is possible to use a larger
config SPL_SIZE_LIMIT_PROVIDE_STACK
hex "SPL image size check: provide stack space before relocation"
depends on SPL_SIZE_LIMIT > 0
- default 0
+ default 0x0
help
If set, this size is reserved in SPL_SIZE_LIMIT check to ensure such
an image does not overflow SRAM if SPL_SIZE_LIMIT describes the size
config TPL_TEXT_BASE
hex "Base address for the .text section of the TPL stage"
- default 0
+ default 0x0
help
The base address for the .text section of the TPL stage.
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_ENV_OFFSET_REDUND=0x540000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="efi-x86_app"
-CONFIG_DEBUG_UART_BASE=0
+CONFIG_DEBUG_UART_BASE=0x0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_VENDOR_EFI=y
CONFIG_TARGET_EFI_APP32=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="efi-x86_app"
-CONFIG_DEBUG_UART_BASE=0
+CONFIG_DEBUG_UART_BASE=0x0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_X86_RUN_64BIT=y
CONFIG_VENDOR_EFI=y
CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
CONFIG_SPL_TEXT_BASE=0x60000000
CONFIG_ROCKCHIP_RK322X=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TARGET_EVB_RK3229=y
CONFIG_SPL_STACK_R_ADDR=0x60600000
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_IMX_WATCHDOG=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_IMX_WATCHDOG=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x0
CONFIG_IMX_WATCHDOG=y
CONFIG_FSPI_CONF_HEADER=y
CONFIG_FSPI_CONF_FILE="fspi_header.bin"
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0x18009ff0
CONFIG_SPL_SIZE_LIMIT=0x20000
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3f0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_WDT=y
CONFIG_WDT_SL28CPLD=y
CONFIG_WDT_SP805=y
-CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
CONFIG_EFI_SET_TIME=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion-haikou"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ROCKCHIP_RK3368=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_ROC_RK3308_CC=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
CONFIG_DM_RESET=y
CONFIG_PRE_CON_BUF_ADDR=0x100000
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX64=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_DM_RESET=y
CONFIG_PRE_CON_BUF_ADDR=0xf0000
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_DM_RESET=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX_SPL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX_SPL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_PCI=y
CONFIG_SANDBOX_SPL=y
CONFIG_ZYNQMP_IPI=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL_STACK=0xfffffffc
CONFIG_SPL_SIZE_LIMIT=0x2a000
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x1E80000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
config SYS_ATA_BASE_ADDR
hex "Base address of IDE controller"
- default 0
+ default 0x0
help
This is the address of the IDE controller, from which other addresses
are calculated. Each bus is at a fixed offset from this address,
ROCKCHIP_RK3399
default 0x280000 if ROCKCHIP_RK3368
default 0x100000 if ARCH_ZYNQMP
- default 0 if SANDBOX
+ default 0x0 if SANDBOX
help
The fastboot protocol requires a large memory buffer for
downloads. Define this to the starting RAM address to use for
config SYS_MXC_I2C1_SLAVE
hex "I2C1 Slave"
- default 0
+ default 0x0
help
MXC I2C1 Slave
endif
config SYS_MXC_I2C2_SLAVE
hex "I2C2 Slave"
- default 0
+ default 0x0
help
MXC I2C2 Slave
endif
config SYS_MXC_I2C3_SLAVE
hex "I2C3 Slave"
- default 0
+ default 0x0
help
MXC I2C3 Slave
endif
config SYS_MXC_I2C4_SLAVE
hex "I2C4 Slave"
- default 0
+ default 0x0
help
MXC I2C4 Slave
endif
config SYS_MXC_I2C5_SLAVE
hex "I2C5 Slave"
- default 0
+ default 0x0
help
MXC I2C5 Slave
endif
config SYS_MXC_I2C6_SLAVE
hex "I2C6 Slave"
- default 0
+ default 0x0
help
MXC I2C6 Slave
endif
config SYS_MXC_I2C7_SLAVE
hex "I2C7 Slave"
- default 0
+ default 0x0
help
MXC I2C7 Slave
endif
config SYS_MXC_I2C8_SLAVE
hex "I2C8 Slave"
- default 0
+ default 0x0
help
MXC I2C8 Slave
endif
config SYS_I2C_EEPROM_ADDR
hex "Chip address of the EEPROM device"
depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
- default 0
+ default 0x0
if I2C_EEPROM
config DEBUG_UART_BASE
hex "Base address of UART"
depends on DEBUG_UART
- default 0 if DEBUG_SBI_CONSOLE
- default 0 if DEBUG_UART_SANDBOX
+ default 0x0 if DEBUG_SBI_CONSOLE
+ default 0x0 if DEBUG_UART_SANDBOX
default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP
default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ
help
config SYS_SDMR
hex "SDMR Value"
depends on MPC8XX_CONS
- default 0
+ default 0x0
endif
config SDP_LOADADDR
hex "Default load address at SDP_WRITE and SDP_JUMP"
- default 0
+ default 0x0
# Selected by UDC drivers that support high-speed operation.
config USB_GADGET_DUALSPEED
hex "Default framebuffer size to use if no drivers request it"
default 0x1000000 if X86
default 0x800000 if !X86 && VIDEO_BOCHS
- default 0 if !X86 && !VIDEO_BOCHS
+ default 0x0 if !X86 && !VIDEO_BOCHS
help
Generally, video drivers request the amount of memory they need for
the frame buffer when they are bound, by setting the size field in
hex "Default framebuffer size to use if no drivers request it at SPL"
default 0x1000000 if X86
default 0x800000 if !X86 && VIDEO_BOCHS
- default 0 if !X86 && !VIDEO_BOCHS
+ default 0x0 if !X86 && !VIDEO_BOCHS
help
Generally, video drivers request the amount of memory they need for
the frame buffer when they are bound, by setting the size field in
default 0xE0000 if ARCH_ZYNQ
default 0x1E00000 if ARCH_ZYNQMP
default 0x7F40000 if ARCH_VERSAL || ARCH_VERSAL_NET
- default 0 if ARC
+ default 0x0 if ARC
default 0x140000 if ARCH_AT91
default 0x260000 if ARCH_OMAP2PLUS
default 0x1080000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH
depends on (ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
ENV_IS_IN_SPI_FLASH) && SYS_REDUNDAND_ENVIRONMENT
default 0x10C0000 if MICROBLAZE
- default 0
+ default 0x0
help
Offset from the start of the device (or partition) of the redundant
environment location.
config OF_LIBFDT_ASSUME_MASK
hex "Mask of conditions to assume for libfdt"
depends on OF_LIBFDT || FIT
- default 0
+ default 0x0
help
Use this to change the assumptions made by libfdt about the
device tree it is working with. A value of 0 means that no assumptions