mips: traps: Set WG bit in EBase register on Octeon

WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 7538e6b2e0bf62c608cdb1a3a74141cbfc42dee2..17381301ec9e8314f8339ca92866bea75e779809 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -366,6 +366,7 @@
  * Bits in the coprocessor 0 EBase register.
  */
 #define EBASE_CPUNUM           0x3ff
+#define EBASE_WG               (_ULCAST_(1) << 11)
 
 /*
  * Bits in the coprocessor 0 config register.

diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index b1ae02fcab8abd064b6a0000c017c6cc0a58f438..6ff9d20bd611499812e1c094937288fd2139dd63 100644 (file)
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -108,6 +108,10 @@ void trap_init(ulong reloc_addr)
 
        saved_ebase = read_c0_ebase() & 0xfffff000;
 
+       /* Set WG bit on Octeon to enable writing to bits 63:30 */
+       if (IS_ENABLED(CONFIG_ARCH_OCTEON))
+               ebase |= EBASE_WG;
+
        write_c0_ebase(ebase);
        clear_c0_status(ST0_BEV);
        execution_hazard_barrier();