OMAP3: Fix CKE1 MUX setting to allow self-refresh

The Beagle rev Cx and Overo boards are using both SDRC CSes. The MUX
setting is needed for the second CS clock signal to allow the 2 RAM
parts to be put in self-refresh correctly. This also works on rev B
Beagle boards with 128M of RAM.

From: Steve Sakoman <steve@sakoman.com>
From: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>

diff --git a/board/omap3/beagle/beagle.h b/board/omap3/beagle/beagle.h
index 324ec66fbeccea6ce0058f809bb62135670891a4..3a0f907d77a38b127aa4f46d9a5f91d030fbae27 100644 (file)
--- a/board/omap3/beagle/beagle.h
+++ b/board/omap3/beagle/beagle.h
@@ -371,7 +371,7 @@ const omap3_sysinfo sysinfo = {
  MUX_VAL(CP(D2D_MBUSFLAG),     (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
  MUX_VAL(CP(D2D_SBUSFLAG),     (IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
  MUX_VAL(CP(SDRC_CKE0),                (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1),                (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+ MUX_VAL(CP(SDRC_CKE1),                (IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 
 #define MUX_BEAGLE_C() \
  MUX_VAL(CP(MCBSP3_DX),                (IEN | PTD | DIS | M4)) /*GPIO_140*/\

diff --git a/board/omap3/overo/overo.h b/board/omap3/overo/overo.h
index b595f6ac3e1b0081cb69e3888770b12c4096bc7e..0b59120a300beb1d2d7cfebfdc76d00997581d24 100644 (file)
--- a/board/omap3/overo/overo.h
+++ b/board/omap3/overo/overo.h
@@ -376,6 +376,6 @@ const omap3_sysinfo sysinfo = {
  MUX_VAL(CP(D2D_MBUSFLAG),     (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
  MUX_VAL(CP(D2D_SBUSFLAG),     (IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
  MUX_VAL(CP(SDRC_CKE0),                (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1),                (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+ MUX_VAL(CP(SDRC_CKE1),                (IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 
 #endif