x86: baytrail: Add documentation for FSP memory-down values

This patch adds the documentation for the memory-down parameters
of the Intel FSP. To configure a board without SPD DDR DIMM but
with onboard DDR chips. The values are taken from the coreboot
header:

	src/soc/intel/fsp_baytrail/chip.h

(git ID da1a70ea from 2016-01-16 as reference).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Andrew Bradford <andrew.bradford@kodakalaris.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
index b44b5b5431f8e65cf7652832314959dc23b8576b..07fa46ef7ef557b095da01cd86b1a255d1160745 100644 (file)
--- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
+++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
@@ -74,12 +74,41 @@ discovered by the FSP and used to setup main memory.
 
        # Integer properties:
 
-       - fsp,dram-speed
+       - fsp,dram-speed:
+         0x0: "800 MHz"
+         0x1: "1066 MHz"
+         0x2: "1333 MHz"
+         0x3: "1600 MHz"
+
        - fsp,dram-type
+         0x0: "DDR3"
+         0x1: "DDR3L"
+         0x2: "DDR3U"
+         0x4: "LPDDR2"
+         0x5: "LPDDR3"
+         0x6: "DDR4"
+
        - fsp,dimm-width
+         0x0: "x8"
+         0x1: "x16"
+         0x2: "x32"
+
        - fsp,dimm-density
+         0x0: "1 Gbit"
+         0x1: "2 Gbit"
+         0x2: "4 Gbit"
+         0x3: "8 Gbit"
+
        - fsp,dimm-bus-width
+         0x0: "8 bits"
+         0x1: "16 bits"
+         0x2: "32 bits"
+         0x3: "64 bits"
+
        - fsp,dimm-sides
+         0x0: "1 rank"
+         0x1: "2 ranks"
+
        - fsp,dimm-tcl
        - fsp,dimm-trpt-rcd
        - fsp,dimm-twr