tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BIT

Even the 8-bit case needs KBCB configured, as pin D7 is located in this
pingroup.

Please note that pingroup ATC seems to come out of reset with its
config set to NAND so one needs to explicitly configure some other
function to this group in order to avoid clashing settings which is
outside the scope of this patch.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c
index 0df4a0738de49d1bfc671bc3c312bde7cc06a68d..44a85c5f1dc98db3965304abc1585971051c3efd 100644 (file)
--- a/arch/arm/mach-tegra/tegra20/funcmux.c
+++ b/arch/arm/mach-tegra/tegra20/funcmux.c
@@ -252,12 +252,14 @@ int funcmux_select(enum periph_id id, int config)
                        break;
                case FUNCMUX_NDFLASH_KBC_8_BIT:
                        pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
+                       pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND);
                        pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
                        pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
                        pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
                        pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
 
                        pinmux_tristate_disable(PMUX_PINGRP_KBCA);
+                       pinmux_tristate_disable(PMUX_PINGRP_KBCB);
                        pinmux_tristate_disable(PMUX_PINGRP_KBCC);
                        pinmux_tristate_disable(PMUX_PINGRP_KBCD);
                        pinmux_tristate_disable(PMUX_PINGRP_KBCE);