Blackfin: use on-chip reset func with newer parts

Turns out the documentation is wrong and doing "RAISE 1" does not result
in a software reset, only a core reset.  So when the on-chip rom has a
functioning reset helper, use it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c
index 9307e9f9e2005670f28549820e82215e989cf240..e23dcc7bae88aa8287ccb908e949fe9248060489 100644 (file)
--- a/arch/blackfin/cpu/reset.c
+++ b/arch/blackfin/cpu/reset.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/bootrom.h>
 #include "cpu.h"
 
 /* A system soft reset makes external memory unusable so force
@@ -29,46 +30,40 @@ static void bfin_reset(void)
         */
        __builtin_bfin_ssync();
 
-       /* The bootrom checks to see how it was reset and will
-        * automatically perform a software reset for us when
-        * it starts executing after the core reset.
-        */
-       if (ANOMALY_05000353 || ANOMALY_05000386) {
-               /* Initiate System software reset. */
-               bfin_write_SWRST(0x7);
+       /* Initiate System software reset. */
+       bfin_write_SWRST(0x7);
 
-               /* Due to the way reset is handled in the hardware, we need
-                * to delay for 10 SCLKS.  The only reliable way to do this is
-                * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
-                * we'll assume worse case which is a 1:15 ratio.
-                */
-               asm(
-                       "LSETUP (1f, 1f) LC0 = %0\n"
-                       "1: nop;"
-                       :
-                       : "a" (15 * 10)
-                       : "LC0", "LB0", "LT0"
-               );
+       /* Due to the way reset is handled in the hardware, we need
+        * to delay for 10 SCLKS.  The only reliable way to do this is
+        * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
+        * we'll assume worse case which is a 1:15 ratio.
+        */
+       asm(
+               "LSETUP (1f, 1f) LC0 = %0\n"
+               "1: nop;"
+               :
+               : "a" (15 * 10)
+               : "LC0", "LB0", "LT0"
+       );
 
-               /* Clear System software reset */
-               bfin_write_SWRST(0);
+       /* Clear System software reset */
+       bfin_write_SWRST(0);
 
-               /* The BF526 ROM will crash during reset */
+       /* The BF526 ROM will crash during reset */
 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-               bfin_read_SWRST();
+       bfin_read_SWRST();
 #endif
 
-               /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
-                * though as the System state is all reset now.
-                */
-               asm(
-                       "LSETUP (1f, 1f) LC1 = %0\n"
-                       "1: nop;"
-                       :
-                       : "a" (15 * 1)
-                       : "LC1", "LB1", "LT1"
-               );
-       }
+       /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
+        * though as the System state is all reset now.
+        */
+       asm(
+               "LSETUP (1f, 1f) LC1 = %0\n"
+               "1: nop;"
+               :
+               : "a" (15 * 1)
+               : "LC1", "LB1", "LT1"
+       );
 
        while (1)
                /* Issue core reset */
@@ -84,7 +79,10 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        if (board_reset)
                board_reset();
-       while (1)
-               asm("jump (%0);" : : "a" (bfin_reset));
+       if (ANOMALY_05000353 || ANOMALY_05000386)
+               while (1)
+                       asm("jump (%0);" : : "a" (bfin_reset));
+       else
+               bfrom_SoftReset((void *)(L1_SRAM_SCRATCH_END - 20));
        return 0;
 }