]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
pinctrl: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux...
authorMarek Vasut <marek.vasut+renesas@mailbox.org>
Thu, 26 Jan 2023 20:01:37 +0000 (21:01 +0100)
committerMarek Vasut <marek.vasut+renesas@gmail.com>
Thu, 2 Feb 2023 00:49:20 +0000 (01:49 +0100)
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
drivers/pinctrl/renesas/pfc-r8a7791.c

index 7c8db5dc2cb77cac28ccdad3731c6eedbc7e0369..219333106fc6eafceffe4820530bca1d21413428 100644 (file)
  * which case they support both 3.3V and 1.8V signalling.
  */
 #define CPU_ALL_GP(fn, sfx)                                            \
-       PORT_GP_32(0, fn, sfx),                                         \
-       PORT_GP_26(1, fn, sfx),                                         \
-       PORT_GP_32(2, fn, sfx),                                         \
-       PORT_GP_32(3, fn, sfx),                                         \
-       PORT_GP_32(4, fn, sfx),                                         \
-       PORT_GP_32(5, fn, sfx),                                         \
-       PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
-       PORT_GP_1(6, 24, fn, sfx),                                      \
-       PORT_GP_1(6, 25, fn, sfx),                                      \
-       PORT_GP_1(6, 26, fn, sfx),                                      \
-       PORT_GP_1(6, 27, fn, sfx),                                      \
-       PORT_GP_1(6, 28, fn, sfx),                                      \
-       PORT_GP_1(6, 29, fn, sfx),                                      \
-       PORT_GP_1(6, 30, fn, sfx),                                      \
-       PORT_GP_1(6, 31, fn, sfx),                                      \
-       PORT_GP_26(7, fn, sfx)
+       PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
+       PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
+       PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
+       PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
+       PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
+       PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
+       PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),              \
+       PORT_GP_1(7, 7, fn, sfx),                                       \
+       PORT_GP_1(7, 8, fn, sfx),                                       \
+       PORT_GP_1(7, 9, fn, sfx),                                       \
+       PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),          \
+       PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
+
+#define CPU_ALL_NOGP(fn)                                               \
+       PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN),        \
+       PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP),         \
+       PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP),         \
+       PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),           \
+       PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),           \
+       PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),           \
+       PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
 
 enum {
        PINMUX_RESERVED = 0,
@@ -209,11 +237,11 @@ enum {
        FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
        FN_SCIFA2_RXD, FN_FMIN_E,
        FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
-       FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
-       FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
-       FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
-       FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
-       FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
+       FN_IRQ0, FN_SCIFB1_RXD_D,
+       FN_IRQ1, FN_SCIFB1_SCK_C,
+       FN_IRQ2, FN_SCIFB1_TXD_D,
+       FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E,
+       FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
        FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
        FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
        FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
@@ -581,12 +609,12 @@ enum {
        AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
        SCIFA2_RXD_MARK, FMIN_E_MARK,
        AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
-       IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
-       IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
-       IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
-       IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
+       IRQ0_MARK, SCIFB1_RXD_D_MARK,
+       IRQ1_MARK, SCIFB1_SCK_C_MARK,
+       IRQ2_MARK, SCIFB1_TXD_D_MARK,
+       IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK,
        IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
-       MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
+       MSIOF2_RXD_E_MARK,
        IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
        IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
        I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
@@ -1115,22 +1143,17 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
        PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
        PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
-       PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
        PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
        PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
-       PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
        PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
        PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
-       PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
        PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
        PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
        PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
-       PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
        PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
        PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
        PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
        PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
-       PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
        PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
        PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
        PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
@@ -1699,8 +1722,17 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
 };
 
+/*
+ * Pins not associated with a GPIO port.
+ */
+enum {
+       GP_ASSIGN_LAST(),
+       NOGP_ALL(),
+};
+
 static const struct sh_pfc_pin pinmux_pins[] = {
        PINMUX_GPIO_GP_ALL(),
+       PINMUX_NOGP_ALL(),
 };
 
 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
@@ -2269,13 +2301,6 @@ static const unsigned int hscif1_data_d_pins[] = {
 static const unsigned int hscif1_data_d_mux[] = {
        HRX1_D_MARK, HTX1_D_MARK,
 };
-static const unsigned int hscif1_data_e_pins[] = {
-       /* RX, TX */
-       RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
-};
-static const unsigned int hscif1_data_e_mux[] = {
-       HRX1_C_MARK, HTX1_C_MARK,
-};
 static const unsigned int hscif1_clk_e_pins[] = {
        /* SCK */
        RCAR_GP_PIN(2, 6),
@@ -2570,40 +2595,25 @@ static const unsigned int mlb_3pin_mux[] = {
 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
 
 /* - MMCIF ------------------------------------------------------------------ */
-static const unsigned int mmc_data1_pins[] = {
-       /* D[0] */
-       RCAR_GP_PIN(6, 18),
-};
-static const unsigned int mmc_data1_mux[] = {
-       MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
-       /* D[0:3] */
-       RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
-       RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
-};
-static const unsigned int mmc_data4_mux[] = {
-       MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
-};
-static const unsigned int mmc_data8_pins[] = {
+static const unsigned int mmc_data_pins[] = {
        /* D[0:7] */
        RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
        RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
        RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
        RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
 };
-static const unsigned int mmc_data8_mux[] = {
+static const unsigned int mmc_data_mux[] = {
        MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
        MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
 };
-static const unsigned int mmc_data8_b_pins[] = {
+static const unsigned int mmc_data_b_pins[] = {
        /* D[0:7] */
        RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
        RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
        RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
        RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
 };
-static const unsigned int mmc_data8_b_mux[] = {
+static const unsigned int mmc_data_b_mux[] = {
        MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
        MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
 };
@@ -3191,19 +3201,12 @@ static const unsigned int qspi_ctrl_pins[] = {
 static const unsigned int qspi_ctrl_mux[] = {
        SPCLK_MARK, SSL_MARK,
 };
-static const unsigned int qspi_data2_pins[] = {
-       /* MOSI_IO0, MISO_IO1 */
-       RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int qspi_data2_mux[] = {
-       MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
+static const unsigned int qspi_data_pins[] = {
        /* MOSI_IO0, MISO_IO1, IO2, IO3 */
        RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
        RCAR_GP_PIN(1, 8),
 };
-static const unsigned int qspi_data4_mux[] = {
+static const unsigned int qspi_data_mux[] = {
        MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
 };
 
@@ -3214,19 +3217,12 @@ static const unsigned int qspi_ctrl_b_pins[] = {
 static const unsigned int qspi_ctrl_b_mux[] = {
        SPCLK_B_MARK, SSL_B_MARK,
 };
-static const unsigned int qspi_data2_b_pins[] = {
-       /* MOSI_IO0, MISO_IO1 */
-       RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
-};
-static const unsigned int qspi_data2_b_mux[] = {
-       MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
-};
-static const unsigned int qspi_data4_b_pins[] = {
+static const unsigned int qspi_data_b_pins[] = {
        /* MOSI_IO0, MISO_IO1, IO2, IO3 */
        RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
        RCAR_GP_PIN(6, 4),
 };
-static const unsigned int qspi_data4_b_mux[] = {
+static const unsigned int qspi_data_b_mux[] = {
        MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
 };
 /* - SCIF0 ------------------------------------------------------------------ */
@@ -3787,19 +3783,12 @@ static const unsigned int scif_clk_b_mux[] = {
 };
 
 /* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
-       /* D0 */
-       RCAR_GP_PIN(6, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
-       SD0_DATA0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
        /* D[0:3] */
        RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
        RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
 };
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
        SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
@@ -3824,19 +3813,12 @@ static const unsigned int sdhi0_wp_mux[] = {
        SD0_WP_MARK,
 };
 /* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
-       /* D0 */
-       RCAR_GP_PIN(6, 10),
-};
-static const unsigned int sdhi1_data1_mux[] = {
-       SD1_DATA0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
        /* D[0:3] */
        RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
        RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
 };
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
        SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
@@ -3861,19 +3843,12 @@ static const unsigned int sdhi1_wp_mux[] = {
        SD1_WP_MARK,
 };
 /* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
-       /* D0 */
-       RCAR_GP_PIN(6, 18),
-};
-static const unsigned int sdhi2_data1_mux[] = {
-       SD2_DATA0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
        /* D[0:3] */
        RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
        RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
 };
-static const unsigned int sdhi2_data4_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
        SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
@@ -4196,43 +4171,39 @@ static const unsigned int usb1_mux[] = {
        USB1_OVC_MARK,
 };
 /* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
-       .data24 = {
-               /* B */
-               RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
-               RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
-               RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
-               RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-               /* G */
-               RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
-               RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
-               RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
-               RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
-               /* R */
-               RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
-               RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
-               RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
-               RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
-       },
+static const unsigned int vin0_data_pins[] = {
+       /* B */
+       RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
+       RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
+       RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+       RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+       /* G */
+       RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
+       RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+       RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
+       RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
+       /* R */
+       RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
+       RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
+       RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
+       RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
 };
-static const union vin_data vin0_data_mux = {
-       .data24 = {
-               /* B */
-               VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
-               VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
-               VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
-               VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
-               /* G */
-               VI0_G0_MARK, VI0_G1_MARK,
-               VI0_G2_MARK, VI0_G3_MARK,
-               VI0_G4_MARK, VI0_G5_MARK,
-               VI0_G6_MARK, VI0_G7_MARK,
-               /* R */
-               VI0_R0_MARK, VI0_R1_MARK,
-               VI0_R2_MARK, VI0_R3_MARK,
-               VI0_R4_MARK, VI0_R5_MARK,
-               VI0_R6_MARK, VI0_R7_MARK,
-       },
+static const unsigned int vin0_data_mux[] = {
+       /* B */
+       VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+       VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+       VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+       VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+       /* G */
+       VI0_G0_MARK, VI0_G1_MARK,
+       VI0_G2_MARK, VI0_G3_MARK,
+       VI0_G4_MARK, VI0_G5_MARK,
+       VI0_G6_MARK, VI0_G7_MARK,
+       /* R */
+       VI0_R0_MARK, VI0_R1_MARK,
+       VI0_R2_MARK, VI0_R3_MARK,
+       VI0_R4_MARK, VI0_R5_MARK,
+       VI0_R6_MARK, VI0_R7_MARK,
 };
 static const unsigned int vin0_data18_pins[] = {
        /* B */
@@ -4327,43 +4298,39 @@ static const unsigned int vin1_clk_pins[] = {
 static const unsigned int vin1_clk_mux[] = {
        VI1_CLK_MARK,
 };
-static const union vin_data vin1_data_b_pins = {
-       .data24 = {
-               /* B */
-               RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
-               RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-               RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-               RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-               /* G */
-               RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
-               RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
-               RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
-               RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
-               /* R */
-               RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
-               RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-               RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-               RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-       },
+static const unsigned int vin1_data_b_pins[] = {
+       /* B */
+       RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+       RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+       RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+       RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+       /* G */
+       RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+       RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+       RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+       RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
+       /* R */
+       RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
+       RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+       RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+       RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
 };
-static const union vin_data vin1_data_b_mux = {
-       .data24 = {
-               /* B */
-               VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
-               VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
-               VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
-               VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
-               /* G */
-               VI1_G0_B_MARK, VI1_G1_B_MARK,
-               VI1_G2_B_MARK, VI1_G3_B_MARK,
-               VI1_G4_B_MARK, VI1_G5_B_MARK,
-               VI1_G6_B_MARK, VI1_G7_B_MARK,
-               /* R */
-               VI1_R0_B_MARK, VI1_R1_B_MARK,
-               VI1_R2_B_MARK, VI1_R3_B_MARK,
-               VI1_R4_B_MARK, VI1_R5_B_MARK,
-               VI1_R6_B_MARK, VI1_R7_B_MARK,
-       },
+static const unsigned int vin1_data_b_mux[] = {
+       /* B */
+       VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
+       VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
+       VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
+       VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
+       /* G */
+       VI1_G0_B_MARK, VI1_G1_B_MARK,
+       VI1_G2_B_MARK, VI1_G3_B_MARK,
+       VI1_G4_B_MARK, VI1_G5_B_MARK,
+       VI1_G6_B_MARK, VI1_G7_B_MARK,
+       /* R */
+       VI1_R0_B_MARK, VI1_R1_B_MARK,
+       VI1_R2_B_MARK, VI1_R3_B_MARK,
+       VI1_R4_B_MARK, VI1_R5_B_MARK,
+       VI1_R6_B_MARK, VI1_R7_B_MARK,
 };
 static const unsigned int vin1_data18_b_pins[] = {
        /* B */
@@ -4522,7 +4489,7 @@ static const struct {
                SH_PFC_PIN_GROUP(hscif1_clk_c),
                SH_PFC_PIN_GROUP(hscif1_ctrl_c),
                SH_PFC_PIN_GROUP(hscif1_data_d),
-               SH_PFC_PIN_GROUP(hscif1_data_e),
+               SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c),
                SH_PFC_PIN_GROUP(hscif1_clk_e),
                SH_PFC_PIN_GROUP(hscif1_ctrl_e),
                SH_PFC_PIN_GROUP(hscif2_data),
@@ -4562,10 +4529,10 @@ static const struct {
                SH_PFC_PIN_GROUP(intc_irq1),
                SH_PFC_PIN_GROUP(intc_irq2),
                SH_PFC_PIN_GROUP(intc_irq3),
-               SH_PFC_PIN_GROUP(mmc_data1),
-               SH_PFC_PIN_GROUP(mmc_data4),
-               SH_PFC_PIN_GROUP(mmc_data8),
-               SH_PFC_PIN_GROUP(mmc_data8_b),
+               BUS_DATA_PIN_GROUP(mmc_data, 1),
+               BUS_DATA_PIN_GROUP(mmc_data, 4),
+               BUS_DATA_PIN_GROUP(mmc_data, 8),
+               BUS_DATA_PIN_GROUP(mmc_data, 8, _b),
                SH_PFC_PIN_GROUP(mmc_ctrl),
                SH_PFC_PIN_GROUP(msiof0_clk),
                SH_PFC_PIN_GROUP(msiof0_sync),
@@ -4649,11 +4616,11 @@ static const struct {
                SH_PFC_PIN_GROUP(pwm5_b),
                SH_PFC_PIN_GROUP(pwm6),
                SH_PFC_PIN_GROUP(qspi_ctrl),
-               SH_PFC_PIN_GROUP(qspi_data2),
-               SH_PFC_PIN_GROUP(qspi_data4),
+               BUS_DATA_PIN_GROUP(qspi_data, 2),
+               BUS_DATA_PIN_GROUP(qspi_data, 4),
                SH_PFC_PIN_GROUP(qspi_ctrl_b),
-               SH_PFC_PIN_GROUP(qspi_data2_b),
-               SH_PFC_PIN_GROUP(qspi_data4_b),
+               BUS_DATA_PIN_GROUP(qspi_data, 2, _b),
+               BUS_DATA_PIN_GROUP(qspi_data, 4, _b),
                SH_PFC_PIN_GROUP(scif0_data),
                SH_PFC_PIN_GROUP(scif0_data_b),
                SH_PFC_PIN_GROUP(scif0_data_c),
@@ -4731,18 +4698,18 @@ static const struct {
                SH_PFC_PIN_GROUP(scifb2_data_d),
                SH_PFC_PIN_GROUP(scif_clk),
                SH_PFC_PIN_GROUP(scif_clk_b),
-               SH_PFC_PIN_GROUP(sdhi0_data1),
-               SH_PFC_PIN_GROUP(sdhi0_data4),
+               BUS_DATA_PIN_GROUP(sdhi0_data, 1),
+               BUS_DATA_PIN_GROUP(sdhi0_data, 4),
                SH_PFC_PIN_GROUP(sdhi0_ctrl),
                SH_PFC_PIN_GROUP(sdhi0_cd),
                SH_PFC_PIN_GROUP(sdhi0_wp),
-               SH_PFC_PIN_GROUP(sdhi1_data1),
-               SH_PFC_PIN_GROUP(sdhi1_data4),
+               BUS_DATA_PIN_GROUP(sdhi1_data, 1),
+               BUS_DATA_PIN_GROUP(sdhi1_data, 4),
                SH_PFC_PIN_GROUP(sdhi1_ctrl),
                SH_PFC_PIN_GROUP(sdhi1_cd),
                SH_PFC_PIN_GROUP(sdhi1_wp),
-               SH_PFC_PIN_GROUP(sdhi2_data1),
-               SH_PFC_PIN_GROUP(sdhi2_data4),
+               BUS_DATA_PIN_GROUP(sdhi2_data, 1),
+               BUS_DATA_PIN_GROUP(sdhi2_data, 4),
                SH_PFC_PIN_GROUP(sdhi2_ctrl),
                SH_PFC_PIN_GROUP(sdhi2_cd),
                SH_PFC_PIN_GROUP(sdhi2_wp),
@@ -4780,13 +4747,13 @@ static const struct {
                SH_PFC_PIN_GROUP(tpu_to3),
                SH_PFC_PIN_GROUP(usb0),
                SH_PFC_PIN_GROUP(usb1),
-               VIN_DATA_PIN_GROUP(vin0_data, 24),
-               VIN_DATA_PIN_GROUP(vin0_data, 20),
+               BUS_DATA_PIN_GROUP(vin0_data, 24),
+               BUS_DATA_PIN_GROUP(vin0_data, 20),
                SH_PFC_PIN_GROUP(vin0_data18),
-               VIN_DATA_PIN_GROUP(vin0_data, 16),
-               VIN_DATA_PIN_GROUP(vin0_data, 12),
-               VIN_DATA_PIN_GROUP(vin0_data, 10),
-               VIN_DATA_PIN_GROUP(vin0_data, 8),
+               BUS_DATA_PIN_GROUP(vin0_data, 16),
+               BUS_DATA_PIN_GROUP(vin0_data, 12),
+               BUS_DATA_PIN_GROUP(vin0_data, 10),
+               BUS_DATA_PIN_GROUP(vin0_data, 8),
                SH_PFC_PIN_GROUP(vin0_sync),
                SH_PFC_PIN_GROUP(vin0_field),
                SH_PFC_PIN_GROUP(vin0_clkenb),
@@ -4796,13 +4763,13 @@ static const struct {
                SH_PFC_PIN_GROUP(vin1_field),
                SH_PFC_PIN_GROUP(vin1_clkenb),
                SH_PFC_PIN_GROUP(vin1_clk),
-               VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
-               VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
+               BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
+               BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
                SH_PFC_PIN_GROUP(vin1_data18_b),
-               VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
-               VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
-               VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
-               VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
+               BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
+               BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
+               BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
+               BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
                SH_PFC_PIN_GROUP(vin1_sync_b),
                SH_PFC_PIN_GROUP(vin1_field_b),
                SH_PFC_PIN_GROUP(vin1_clkenb_b),
@@ -5722,11 +5689,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_7_0_FN, FN_IP15_17_15 ))
        },
        { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
-                            GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
+                            GROUP(-1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
                                   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
                             GROUP(
-               /* IP0_31 [1] */
-               0, 0,
+               /* IP0_31 [1] RESERVED */
                /* IP0_30_29 [2] */
                FN_A6, FN_MSIOF1_SCK,
                0, 0,
@@ -5819,10 +5785,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
-                            GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
+                            GROUP(-2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
                             GROUP(
-               /* IP2_31_30 [2] */
-               0, 0, 0, 0,
+               /* IP2_31_30 [2] RESERVED */
                /* IP2_29_27 [3] */
                FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
                FN_ATAG0_N, 0, FN_EX_WAIT1,
@@ -5856,10 +5821,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
-                            GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
+                            GROUP(-1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
                             GROUP(
-               /* IP3_31 [1] */
-               0, 0,
+               /* IP3_31 [1] RESERVED */
                /* IP3_30_28 [3] */
                FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
                FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
@@ -5895,11 +5859,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
-                            GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
+                            GROUP(-1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
                                   3, 3, 2),
                             GROUP(
-               /* IP4_31 [1] */
-               0, 0,
+               /* IP4_31 [1] RESERVED */
                /* IP4_30_28 [3] */
                FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
                FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
@@ -5979,10 +5942,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
-                            GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
+                            GROUP(-2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
                             GROUP(
-               /* IP6_31_30 [2] */
-               0, 0, 0, 0,
+               /* IP6_31_30 [2] RESERVED */
                /* IP6_29_27 [3] */
                FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
                FN_GPS_SIGN_C, FN_GPS_SIGN_D,
@@ -5999,15 +5961,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
                /* IP6_18_16 [3] */
                FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
-               FN_INTC_IRQ4_N, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP6_15_14 [2] */
-               FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
+               FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0,
                /* IP6_13_12 [2] */
-               FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
+               FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0,
                /* IP6_11_10 [2] */
-               FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
+               FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0,
                /* IP6_9_8 [2] */
-               FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
+               FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0,
                /* IP6_7_6 [2] */
                FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
                /* IP6_5_3 [3] */
@@ -6020,10 +5982,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
-                            GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
+                            GROUP(-2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
                             GROUP(
-               /* IP7_31_30 [2] */
-               0, 0, 0, 0,
+               /* IP7_31_30 [2] RESERVED */
                /* IP7_29_27 [3] */
                FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
                FN_SCIFA1_SCK, FN_SSI_SCK78_B,
@@ -6062,10 +6023,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
-                            GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
+                            GROUP(-1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
                             GROUP(
-               /* IP8_31 [1] */
-               0, 0,
+               /* IP8_31 [1] RESERVED */
                /* IP8_30_28 [3] */
                FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
                0, 0, 0,
@@ -6237,10 +6197,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_I2C1_SDA_D, 0, 0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
-                            GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
+                            GROUP(-2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
                             GROUP(
-               /* IP12_31_30 [2] */
-               0, 0, 0, 0,
+               /* IP12_31_30 [2] RESERVED */
                /* IP12_29_27 [3] */
                FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
                FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
@@ -6279,11 +6238,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
-                            GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
+                            GROUP(-1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
                                   1, 1, 1, 3, 2, 2, 3),
                             GROUP(
-               /* IP13_31 [1] */
-               0, 0,
+               /* IP13_31 [1] RESERVED */
                /* IP13_30_28 [3] */
                FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
                0, 0, 0, 0,
@@ -6376,10 +6334,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
-                            GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
+                            GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
                             GROUP(
-               /* IP15_31_30 [2] */
-               0, 0, 0, 0,
+               /* IP15_31_30 [2] RESERVED */
                /* IP15_29_27 [3] */
                FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
                FN_CAN0_TX_B, FN_VI1_DATA5_C,
@@ -6418,23 +6375,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
        },
        { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
-                            GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
+                            GROUP(-20, 2, 2, 2, 3, 3),
                             GROUP(
-               /* IP16_31_28 [4] */
-               0, 0, 0, 0, 0, 0, 0, 0,
-               0, 0, 0, 0, 0, 0, 0, 0,
-               /* IP16_27_24 [4] */
-               0, 0, 0, 0, 0, 0, 0, 0,
-               0, 0, 0, 0, 0, 0, 0, 0,
-               /* IP16_23_20 [4] */
-               0, 0, 0, 0, 0, 0, 0, 0,
-               0, 0, 0, 0, 0, 0, 0, 0,
-               /* IP16_19_16 [4] */
-               0, 0, 0, 0, 0, 0, 0, 0,
-               0, 0, 0, 0, 0, 0, 0, 0,
-               /* IP16_15_12 [4] */
-               0, 0, 0, 0, 0, 0, 0, 0,
-               0, 0, 0, 0, 0, 0, 0, 0,
+               /* RESERVED [20] */
                /* IP16_11_10 [2] */
                FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
                /* IP16_9_8 [2] */
@@ -6451,11 +6394,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, 0, ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
-                            GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
-                                  2, 2, 1, 2, 2, 2),
+                            GROUP(-1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, -2,
+                                  2, -2, 1, 2, 2, 2),
                             GROUP(
                /* RESERVED [1] */
-               0, 0,
                /* SEL_SCIF1 [2] */
                FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
                /* SEL_SCIFB [2] */
@@ -6482,11 +6424,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
                0, 0, 0,
                /* RESERVED [2] */
-               0, 0, 0, 0,
                /* SEL_VI1 [2] */
                FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
                /* RESERVED [2] */
-               0, 0, 0, 0,
                /* SEL_TMU [1] */
                FN_SEL_TMU1_0, FN_SEL_TMU1_1,
                /* SEL_LBS [2] */
@@ -6497,15 +6437,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
-                            GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
-                                  1, 2, 2, 2, 1, 1, 1),
+                            GROUP(3, -1, 1, 3, 2, -1, 1, 2, -2, 1, 3, 2,
+                                  -1, 2, 2, 2, 1, -1, 1),
                             GROUP(
                /* SEL_SCIF0 [3] */
                FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
                FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
                0, 0, 0,
                /* RESERVED [1] */
-               0, 0,
                /* SEL_SCIF [1] */
                FN_SEL_SCIF_0, FN_SEL_SCIF_1,
                /* SEL_CAN0 [3] */
@@ -6515,13 +6454,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* SEL_CAN1 [2] */
                FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
                /* RESERVED [1] */
-               0, 0,
                /* SEL_SCIFA2 [1] */
                FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
                /* SEL_SCIF4 [2] */
                FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
                /* RESERVED [2] */
-               0, 0, 0, 0,
                /* SEL_ADG [1] */
                FN_SEL_ADG_0, FN_SEL_ADG_1,
                /* SEL_FM [3] */
@@ -6531,7 +6468,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* SEL_SCIFA5 [2] */
                FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
                /* RESERVED [1] */
-               0, 0,
                /* SEL_GPS [2] */
                FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
                /* SEL_SCIFA4 [2] */
@@ -6541,13 +6477,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* SEL_SIM [1] */
                FN_SEL_SIM_0, FN_SEL_SIM_1,
                /* RESERVED [1] */
-               0, 0,
                /* SEL_SSI8 [1] */
                FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
-                            GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
-                                  3, 2, 2, 2, 1),
+                            GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, -2, 2,
+                                  3, 2, -5),
                             GROUP(
                /* SEL_HSCIF2 [2] */
                FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
@@ -6572,7 +6507,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* SEL_SCIF5 [1] */
                FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
                /* RESERVED [2] */
-               0, 0, 0, 0,
                /* SEL_I2C2 [2] */
                FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
                /* SEL_I2C1 [3] */
@@ -6581,16 +6515,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, 0,
                /* SEL_I2C0 [2] */
                FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
-               /* RESERVED [2] */
-               0, 0, 0, 0,
-               /* RESERVED [2] */
-               0, 0, 0, 0,
-               /* RESERVED [1] */
-               0, 0, ))
+               /* RESERVED [5] */ ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
-                            GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
-                                  1, 1, 2, 2, 2, 2),
+                            GROUP(3, 2, 2, -1, 1, 1, 1, 3, -4, 3, -1,
+                                  1, 1, 2, -6),
                             GROUP(
                /* SEL_SOF1 [3] */
                FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
@@ -6601,7 +6530,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* SEL_DIS [2] */
                FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
                /* RESERVED [1] */
-               0, 0,
                /* SEL_RAD [1] */
                FN_SEL_RAD_0, FN_SEL_RAD_1,
                /* SEL_RCN [1] */
@@ -6613,32 +6541,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
                0, 0, 0,
                /* RESERVED [2] */
-               0, 0, 0, 0,
                /* RESERVED [2] */
-               0, 0, 0, 0,
                /* SEL_SOF2 [3] */
                FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
                FN_SEL_SOF2_3, FN_SEL_SOF2_4,
                0, 0, 0,
                /* RESERVED [1] */
-               0, 0,
                /* SEL_SSI1 [1] */
                FN_SEL_SSI1_0, FN_SEL_SSI1_1,
                /* SEL_SSI0 [1] */
                FN_SEL_SSI0_0, FN_SEL_SSI0_1,
                /* SEL_SSP [2] */
                FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
-               /* RESERVED [2] */
-               0, 0, 0, 0,
-               /* RESERVED [2] */
-               0, 0, 0, 0,
-               /* RESERVED [2] */
-               0, 0, 0, 0, ))
+               /* RESERVED [6] */ ))
        },
        { },
 };
 
-static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
        if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
                return -EINVAL;
@@ -6648,14 +6568,328 @@ static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
        return 31 - (pin & 0x1f);
 }
 
-static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
+static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+       { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
+               [ 0] = RCAR_GP_PIN(1,  4),      /* A20 */
+               [ 1] = RCAR_GP_PIN(1,  5),      /* A21 */
+               [ 2] = RCAR_GP_PIN(1,  6),      /* A22 */
+               [ 3] = RCAR_GP_PIN(1,  7),      /* A23 */
+               [ 4] = RCAR_GP_PIN(1,  8),      /* A24 */
+               [ 5] = RCAR_GP_PIN(6, 31),      /* DU0_DOTCLKIN */
+               [ 6] = RCAR_GP_PIN(0,  0),      /* D0 */
+               [ 7] = RCAR_GP_PIN(0,  1),      /* D1 */
+               [ 8] = RCAR_GP_PIN(0,  2),      /* D2 */
+               [ 9] = RCAR_GP_PIN(0,  3),      /* D3 */
+               [10] = RCAR_GP_PIN(0,  4),      /* D4 */
+               [11] = RCAR_GP_PIN(0,  5),      /* D5 */
+               [12] = RCAR_GP_PIN(0,  6),      /* D6 */
+               [13] = RCAR_GP_PIN(0,  7),      /* D7 */
+               [14] = RCAR_GP_PIN(0,  8),      /* D8 */
+               [15] = RCAR_GP_PIN(0,  9),      /* D9 */
+               [16] = RCAR_GP_PIN(0, 10),      /* D10 */
+               [17] = RCAR_GP_PIN(0, 11),      /* D11 */
+               [18] = RCAR_GP_PIN(0, 12),      /* D12 */
+               [19] = RCAR_GP_PIN(0, 13),      /* D13 */
+               [20] = RCAR_GP_PIN(0, 14),      /* D14 */
+               [21] = RCAR_GP_PIN(0, 15),      /* D15 */
+               [22] = RCAR_GP_PIN(0, 16),      /* A0 */
+               [23] = RCAR_GP_PIN(0, 17),      /* A1 */
+               [24] = RCAR_GP_PIN(0, 18),      /* A2 */
+               [25] = RCAR_GP_PIN(0, 19),      /* A3 */
+               [26] = RCAR_GP_PIN(0, 20),      /* A4 */
+               [27] = RCAR_GP_PIN(0, 21),      /* A5 */
+               [28] = RCAR_GP_PIN(0, 22),      /* A6 */
+               [29] = RCAR_GP_PIN(0, 23),      /* A7 */
+               [30] = RCAR_GP_PIN(0, 24),      /* A8 */
+               [31] = RCAR_GP_PIN(0, 25),      /* A9 */
+       } },
+       { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
+               [ 0] = RCAR_GP_PIN(0, 26),      /* A10 */
+               [ 1] = RCAR_GP_PIN(0, 27),      /* A11 */
+               [ 2] = RCAR_GP_PIN(0, 28),      /* A12 */
+               [ 3] = RCAR_GP_PIN(0, 29),      /* A13 */
+               [ 4] = RCAR_GP_PIN(0, 30),      /* A14 */
+               [ 5] = RCAR_GP_PIN(0, 31),      /* A15 */
+               [ 6] = RCAR_GP_PIN(1,  0),      /* A16 */
+               [ 7] = RCAR_GP_PIN(1,  1),      /* A17 */
+               [ 8] = RCAR_GP_PIN(1,  2),      /* A18 */
+               [ 9] = RCAR_GP_PIN(1,  3),      /* A19 */
+               [10] = PIN_TRST_N,              /* TRST# */
+               [11] = PIN_TCK,                 /* TCK */
+               [12] = PIN_TMS,                 /* TMS */
+               [13] = PIN_TDI,                 /* TDI */
+               [14] = RCAR_GP_PIN(1, 11),      /* CS1#/A26 */
+               [15] = RCAR_GP_PIN(1, 12),      /* EX_CS0# */
+               [16] = RCAR_GP_PIN(1, 13),      /* EX_CS1# */
+               [17] = RCAR_GP_PIN(1, 14),      /* EX_CS2# */
+               [18] = RCAR_GP_PIN(1, 15),      /* EX_CS3# */
+               [19] = RCAR_GP_PIN(1, 16),      /* EX_CS4# */
+               [20] = RCAR_GP_PIN(1, 17),      /* EX_CS5# */
+               [21] = RCAR_GP_PIN(1, 18),      /* BS# */
+               [22] = RCAR_GP_PIN(1, 19),      /* RD# */
+               [23] = RCAR_GP_PIN(1, 20),      /* RD/WR# */
+               [24] = RCAR_GP_PIN(1, 21),      /* WE0# */
+               [25] = RCAR_GP_PIN(1, 22),      /* WE1# */
+               [26] = RCAR_GP_PIN(1, 23),      /* EX_WAIT0 */
+               [27] = RCAR_GP_PIN(1, 24),      /* DREQ0 */
+               [28] = RCAR_GP_PIN(1, 25),      /* DACK0 */
+               [29] = RCAR_GP_PIN(5, 31),      /* SPEEDIN */
+               [30] = RCAR_GP_PIN(2,  0),      /* SSI_SCK0129 */
+               [31] = RCAR_GP_PIN(2,  1),      /* SSI_WS0129 */
+       } },
+       { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
+               [ 0] = RCAR_GP_PIN(2,  2),      /* SSI_SDATA0 */
+               [ 1] = RCAR_GP_PIN(2,  3),      /* SSI_SCK1 */
+               [ 2] = RCAR_GP_PIN(2,  4),      /* SSI_WS1 */
+               [ 3] = RCAR_GP_PIN(2,  5),      /* SSI_SDATA1 */
+               [ 4] = RCAR_GP_PIN(2,  6),      /* SSI_SCK2 */
+               [ 5] = RCAR_GP_PIN(2,  7),      /* SSI_WS2 */
+               [ 6] = RCAR_GP_PIN(2,  8),      /* SSI_SDATA2 */
+               [ 7] = RCAR_GP_PIN(2,  9),      /* SSI_SCK34 */
+               [ 8] = RCAR_GP_PIN(2, 10),      /* SSI_WS34 */
+               [ 9] = RCAR_GP_PIN(2, 11),      /* SSI_SDATA3 */
+               [10] = RCAR_GP_PIN(2, 12),      /* SSI_SCK4 */
+               [11] = RCAR_GP_PIN(2, 13),      /* SSI_WS4 */
+               [12] = RCAR_GP_PIN(2, 14),      /* SSI_SDATA4 */
+               [13] = RCAR_GP_PIN(2, 15),      /* SSI_SCK5 */
+               [14] = RCAR_GP_PIN(2, 16),      /* SSI_WS5 */
+               [15] = RCAR_GP_PIN(2, 17),      /* SSI_SDATA5 */
+               [16] = RCAR_GP_PIN(2, 18),      /* SSI_SCK6 */
+               [17] = RCAR_GP_PIN(2, 19),      /* SSI_WS6 */
+               [18] = RCAR_GP_PIN(2, 20),      /* SSI_SDATA6 */
+               [19] = RCAR_GP_PIN(2, 21),      /* SSI_SCK78 */
+               [20] = RCAR_GP_PIN(2, 22),      /* SSI_WS78 */
+               [21] = RCAR_GP_PIN(2, 23),      /* SSI_SDATA7 */
+               [22] = RCAR_GP_PIN(2, 24),      /* SSI_SDATA8 */
+               [23] = RCAR_GP_PIN(2, 25),      /* SSI_SCK9 */
+               [24] = RCAR_GP_PIN(2, 26),      /* SSI_WS9 */
+               [25] = RCAR_GP_PIN(2, 27),      /* SSI_SDATA9 */
+               [26] = RCAR_GP_PIN(2, 28),      /* AUDIO_CLKA */
+               [27] = RCAR_GP_PIN(2, 29),      /* AUDIO_CLKB */
+               [28] = RCAR_GP_PIN(2, 30),      /* AUDIO_CLKC */
+               [29] = RCAR_GP_PIN(2, 31),      /* AUDIO_CLKOUT */
+               [30] = RCAR_GP_PIN(7, 10),      /* IRQ0 */
+               [31] = RCAR_GP_PIN(7, 11),      /* IRQ1 */
+       } },
+       { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
+               [ 0] = RCAR_GP_PIN(7, 12),      /* IRQ2 */
+               [ 1] = RCAR_GP_PIN(7, 13),      /* IRQ3 */
+               [ 2] = RCAR_GP_PIN(7, 14),      /* IRQ4 */
+               [ 3] = RCAR_GP_PIN(7, 15),      /* IRQ5 */
+               [ 4] = RCAR_GP_PIN(7, 16),      /* IRQ6 */
+               [ 5] = RCAR_GP_PIN(7, 17),      /* IRQ7 */
+               [ 6] = RCAR_GP_PIN(7, 18),      /* IRQ8 */
+               [ 7] = RCAR_GP_PIN(7, 19),      /* IRQ9 */
+               [ 8] = RCAR_GP_PIN(3,  0),      /* DU1_DR0 */
+               [ 9] = RCAR_GP_PIN(3,  1),      /* DU1_DR1 */
+               [10] = RCAR_GP_PIN(3,  2),      /* DU1_DR2 */
+               [11] = RCAR_GP_PIN(3,  3),      /* DU1_DR3 */
+               [12] = RCAR_GP_PIN(3,  4),      /* DU1_DR4 */
+               [13] = RCAR_GP_PIN(3,  5),      /* DU1_DR5 */
+               [14] = RCAR_GP_PIN(3,  6),      /* DU1_DR6 */
+               [15] = RCAR_GP_PIN(3,  7),      /* DU1_DR7 */
+               [16] = RCAR_GP_PIN(3,  8),      /* DU1_DG0 */
+               [17] = RCAR_GP_PIN(3,  9),      /* DU1_DG1 */
+               [18] = RCAR_GP_PIN(3, 10),      /* DU1_DG2 */
+               [19] = RCAR_GP_PIN(3, 11),      /* DU1_DG3 */
+               [20] = RCAR_GP_PIN(3, 12),      /* DU1_DG4 */
+               [21] = RCAR_GP_PIN(3, 13),      /* DU1_DG5 */
+               [22] = RCAR_GP_PIN(3, 14),      /* DU1_DG6 */
+               [23] = RCAR_GP_PIN(3, 15),      /* DU1_DG7 */
+               [24] = RCAR_GP_PIN(3, 16),      /* DU1_DB0 */
+               [25] = RCAR_GP_PIN(3, 17),      /* DU1_DB1 */
+               [26] = RCAR_GP_PIN(3, 18),      /* DU1_DB2 */
+               [27] = RCAR_GP_PIN(3, 19),      /* DU1_DB3 */
+               [28] = RCAR_GP_PIN(3, 20),      /* DU1_DB4 */
+               [29] = RCAR_GP_PIN(3, 21),      /* DU1_DB5 */
+               [30] = RCAR_GP_PIN(3, 22),      /* DU1_DB6 */
+               [31] = RCAR_GP_PIN(3, 23),      /* DU1_DB7 */
+       } },
+       { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
+               [ 0] = RCAR_GP_PIN(3, 24),      /* DU1_DOTCLKIN */
+               [ 1] = RCAR_GP_PIN(3, 25),      /* DU1_DOTCLKOUT0 */
+               [ 2] = RCAR_GP_PIN(3, 26),      /* DU1_DOTCLKOUT1 */
+               [ 3] = RCAR_GP_PIN(3, 27),      /* DU1_EXHSYNC_DU1_HSYNC */
+               [ 4] = RCAR_GP_PIN(3, 28),      /* DU1_EXVSYNC_DU1_VSYNC */
+               [ 5] = RCAR_GP_PIN(3, 29),      /* DU1_EXODDF_DU1_ODDF_DISP_CDE */
+               [ 6] = RCAR_GP_PIN(3, 30),      /* DU1_DISP */
+               [ 7] = RCAR_GP_PIN(3, 31),      /* DU1_CDE */
+               [ 8] = RCAR_GP_PIN(4,  0),      /* VI0_CLK */
+               [ 9] = RCAR_GP_PIN(4,  1),      /* VI0_CLKENB */
+               [10] = RCAR_GP_PIN(4,  2),      /* VI0_FIELD */
+               [11] = RCAR_GP_PIN(4,  3),      /* VI0_HSYNC# */
+               [12] = RCAR_GP_PIN(4,  4),      /* VI0_VSYNC# */
+               [13] = RCAR_GP_PIN(4,  5),      /* VI0_DATA0_VI0_B0 */
+               [14] = RCAR_GP_PIN(4,  6),      /* VI0_DATA1_VI0_B1 */
+               [15] = RCAR_GP_PIN(4,  7),      /* VI0_DATA2_VI0_B2 */
+               [16] = RCAR_GP_PIN(4,  8),      /* VI0_DATA3_VI0_B3 */
+               [17] = RCAR_GP_PIN(4,  9),      /* VI0_DATA4_VI0_B4 */
+               [18] = RCAR_GP_PIN(4, 10),      /* VI0_DATA5_VI0_B5 */
+               [19] = RCAR_GP_PIN(4, 11),      /* VI0_DATA6_VI0_B6 */
+               [20] = RCAR_GP_PIN(4, 12),      /* VI0_DATA7_VI0_B7 */
+               [21] = RCAR_GP_PIN(4, 13),      /* VI0_G0 */
+               [22] = RCAR_GP_PIN(4, 14),      /* VI0_G1 */
+               [23] = RCAR_GP_PIN(4, 15),      /* VI0_G2 */
+               [24] = RCAR_GP_PIN(4, 16),      /* VI0_G3 */
+               [25] = RCAR_GP_PIN(4, 17),      /* VI0_G4 */
+               [26] = RCAR_GP_PIN(4, 18),      /* VI0_G5 */
+               [27] = RCAR_GP_PIN(4, 19),      /* VI0_G6 */
+               [28] = RCAR_GP_PIN(4, 20),      /* VI0_G7 */
+               [29] = RCAR_GP_PIN(4, 21),      /* VI0_R0 */
+               [30] = RCAR_GP_PIN(4, 22),      /* VI0_R1 */
+               [31] = RCAR_GP_PIN(4, 23),      /* VI0_R2 */
+       } },
+       { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
+               [ 0] = RCAR_GP_PIN(4, 24),      /* VI0_R3 */
+               [ 1] = RCAR_GP_PIN(4, 25),      /* VI0_R4 */
+               [ 2] = RCAR_GP_PIN(4, 26),      /* VI0_R5 */
+               [ 3] = RCAR_GP_PIN(4, 27),      /* VI0_R6 */
+               [ 4] = RCAR_GP_PIN(4, 28),      /* VI0_R7 */
+               [ 5] = RCAR_GP_PIN(5,  0),      /* VI1_HSYNC# */
+               [ 6] = RCAR_GP_PIN(5,  1),      /* VI1_VSYNC# */
+               [ 7] = RCAR_GP_PIN(5,  2),      /* VI1_CLKENB */
+               [ 8] = RCAR_GP_PIN(5,  3),      /* VI1_FIELD */
+               [ 9] = RCAR_GP_PIN(5,  4),      /* VI1_CLK */
+               [10] = RCAR_GP_PIN(5,  5),      /* VI1_DATA0 */
+               [11] = RCAR_GP_PIN(5,  6),      /* VI1_DATA1 */
+               [12] = RCAR_GP_PIN(5,  7),      /* VI1_DATA2 */
+               [13] = RCAR_GP_PIN(5,  8),      /* VI1_DATA3 */
+               [14] = RCAR_GP_PIN(5,  9),      /* VI1_DATA4 */
+               [15] = RCAR_GP_PIN(5, 10),      /* VI1_DATA5 */
+               [16] = RCAR_GP_PIN(5, 11),      /* VI1_DATA6 */
+               [17] = RCAR_GP_PIN(5, 12),      /* VI1_DATA7 */
+               [18] = RCAR_GP_PIN(5, 13),      /* ETH_MDIO */
+               [19] = RCAR_GP_PIN(5, 14),      /* ETH_CRS_DV */
+               [20] = RCAR_GP_PIN(5, 15),      /* ETH_RX_ER */
+               [21] = RCAR_GP_PIN(5, 16),      /* ETH_RXD0 */
+               [22] = RCAR_GP_PIN(5, 17),      /* ETH_RXD1 */
+               [23] = RCAR_GP_PIN(5, 18),      /* ETH_LINK */
+               [24] = RCAR_GP_PIN(5, 19),      /* ETH_REFCLK */
+               [25] = RCAR_GP_PIN(5, 20),      /* ETH_TXD1 */
+               [26] = RCAR_GP_PIN(5, 21),      /* ETH_TX_EN */
+               [27] = RCAR_GP_PIN(5, 22),      /* ETH_MAGIC */
+               [28] = RCAR_GP_PIN(5, 23),      /* ETH_TXD0 */
+               [29] = RCAR_GP_PIN(5, 24),      /* ETH_MDC */
+               [30] = RCAR_GP_PIN(5, 25),      /* STP_IVCXO27_0 */
+               [31] = RCAR_GP_PIN(5, 26),      /* STP_ISCLK_0 */
+       } },
+       { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
+               [ 0] = RCAR_GP_PIN(5, 27),      /* STP_ISD_0 */
+               [ 1] = RCAR_GP_PIN(5, 28),      /* STP_ISEN_0 */
+               [ 2] = RCAR_GP_PIN(5, 29),      /* STP_ISSYNC_0 */
+               [ 3] = RCAR_GP_PIN(5, 30),      /* STP_OPWM_0 */
+               [ 4] = RCAR_GP_PIN(6,  0),      /* SD0_CLK */
+               [ 5] = RCAR_GP_PIN(6,  1),      /* SD0_CMD */
+               [ 6] = RCAR_GP_PIN(6,  2),      /* SD0_DATA0 */
+               [ 7] = RCAR_GP_PIN(6,  3),      /* SD0_DATA1 */
+               [ 8] = RCAR_GP_PIN(6,  4),      /* SD0_DATA2 */
+               [ 9] = RCAR_GP_PIN(6,  5),      /* SD0_DATA3 */
+               [10] = RCAR_GP_PIN(6,  6),      /* SD0_CD */
+               [11] = RCAR_GP_PIN(6,  7),      /* SD0_WP */
+               [12] = RCAR_GP_PIN(6,  8),      /* SD2_CLK */
+               [13] = RCAR_GP_PIN(6,  9),      /* SD2_CMD */
+               [14] = RCAR_GP_PIN(6, 10),      /* SD2_DATA0 */
+               [15] = RCAR_GP_PIN(6, 11),      /* SD2_DATA1 */
+               [16] = RCAR_GP_PIN(6, 12),      /* SD2_DATA2 */
+               [17] = RCAR_GP_PIN(6, 13),      /* SD2_DATA3 */
+               [18] = RCAR_GP_PIN(6, 14),      /* SD2_CD */
+               [19] = RCAR_GP_PIN(6, 15),      /* SD2_WP */
+               [20] = RCAR_GP_PIN(6, 16),      /* SD3_CLK */
+               [21] = RCAR_GP_PIN(6, 17),      /* SD3_CMD */
+               [22] = RCAR_GP_PIN(6, 18),      /* SD3_DATA0 */
+               [23] = RCAR_GP_PIN(6, 19),      /* SD3_DATA1 */
+               [24] = RCAR_GP_PIN(6, 20),      /* SD3_DATA2 */
+               [25] = RCAR_GP_PIN(6, 21),      /* SD3_DATA3 */
+               [26] = RCAR_GP_PIN(6, 22),      /* SD3_CD */
+               [27] = RCAR_GP_PIN(6, 23),      /* SD3_WP */
+               [28] = RCAR_GP_PIN(6, 24),      /* MSIOF0_SCK */
+               [29] = RCAR_GP_PIN(6, 25),      /* MSIOF0_SYNC */
+               [30] = RCAR_GP_PIN(6, 26),      /* MSIOF0_TXD */
+               [31] = RCAR_GP_PIN(6, 27),      /* MSIOF0_RXD */
+       } },
+       { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
+               /* PUPR7 pull-up pins */
+               [ 0] = RCAR_GP_PIN(6, 28),      /* MSIOF0_SS1 */
+               [ 1] = RCAR_GP_PIN(6, 29),      /* MSIOF0_SS2 */
+               [ 2] = RCAR_GP_PIN(4, 29),      /* SIM0_RST */
+               [ 3] = RCAR_GP_PIN(4, 30),      /* SIM0_CLK */
+               [ 4] = RCAR_GP_PIN(4, 31),      /* SIM0_D */
+               [ 5] = RCAR_GP_PIN(7, 20),      /* GPS_CLK */
+               [ 6] = RCAR_GP_PIN(7, 21),      /* GPS_SIGN */
+               [ 7] = RCAR_GP_PIN(7, 22),      /* GPS_MAG */
+               [ 8] = RCAR_GP_PIN(7,  0),      /* HCTS0# */
+               [ 9] = RCAR_GP_PIN(7,  1),      /* HRTS0# */
+               [10] = RCAR_GP_PIN(7,  2),      /* HSCK0 */
+               [11] = RCAR_GP_PIN(7,  3),      /* HRX0 */
+               [12] = RCAR_GP_PIN(7,  4),      /* HTX0 */
+               [13] = RCAR_GP_PIN(7,  5),      /* HRX1 */
+               [14] = RCAR_GP_PIN(7,  6),      /* HTX1 */
+               [15] = SH_PFC_PIN_NONE,
+               [16] = SH_PFC_PIN_NONE,
+               [17] = SH_PFC_PIN_NONE,
+               [18] = RCAR_GP_PIN(1,  9),      /* A25 */
+               [19] = SH_PFC_PIN_NONE,
+               [20] = RCAR_GP_PIN(1, 10),      /* CS0# */
+               [21] = RCAR_GP_PIN(7, 23),      /* USB0_PWEN */
+               [22] = RCAR_GP_PIN(7, 24),      /* USB0_OVC */
+               [23] = RCAR_GP_PIN(7, 25),      /* USB1_PWEN */
+               [24] = RCAR_GP_PIN(6, 30),      /* USB1_OVC */
+               [25] = PIN_AVS1,                /* AVS1 */
+               [26] = PIN_AVS2,                /* AVS2 */
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) {
+               /* PUPR7 pull-down pins */
+               [ 0] = SH_PFC_PIN_NONE,
+               [ 1] = SH_PFC_PIN_NONE,
+               [ 2] = SH_PFC_PIN_NONE,
+               [ 3] = SH_PFC_PIN_NONE,
+               [ 4] = SH_PFC_PIN_NONE,
+               [ 5] = SH_PFC_PIN_NONE,
+               [ 6] = SH_PFC_PIN_NONE,
+               [ 7] = SH_PFC_PIN_NONE,
+               [ 8] = SH_PFC_PIN_NONE,
+               [ 9] = SH_PFC_PIN_NONE,
+               [10] = SH_PFC_PIN_NONE,
+               [11] = SH_PFC_PIN_NONE,
+               [12] = SH_PFC_PIN_NONE,
+               [13] = SH_PFC_PIN_NONE,
+               [14] = SH_PFC_PIN_NONE,
+               [15] = SH_PFC_PIN_NONE,
+               [16] = SH_PFC_PIN_NONE,
+               [17] = SH_PFC_PIN_NONE,
+               [18] = SH_PFC_PIN_NONE,
+               [19] = PIN_ASEBRK_N_ACK,        /* ASEBRK#/ACK */
+               [20] = SH_PFC_PIN_NONE,
+               [21] = SH_PFC_PIN_NONE,
+               [22] = SH_PFC_PIN_NONE,
+               [23] = SH_PFC_PIN_NONE,
+               [24] = SH_PFC_PIN_NONE,
+               [25] = SH_PFC_PIN_NONE,
+               [26] = SH_PFC_PIN_NONE,
+               [27] = SH_PFC_PIN_NONE,
+               [28] = SH_PFC_PIN_NONE,
+               [29] = SH_PFC_PIN_NONE,
+               [30] = SH_PFC_PIN_NONE,
+               [31] = SH_PFC_PIN_NONE,
+       } },
+       { /* sentinel */ },
+};
+
+static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
        .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
+       .get_bias = rcar_pinmux_get_bias,
+       .set_bias = rcar_pinmux_set_bias,
 };
 
 #ifdef CONFIG_PINCTRL_PFC_R8A7743
 const struct sh_pfc_soc_info r8a7743_pinmux_info = {
        .name = "r8a77430_pfc",
-       .ops = &r8a7791_pinmux_ops,
+       .ops = &r8a7791_pfc_ops,
        .unlock_reg = 0xe6060000, /* PMMR */
 
        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6668,6 +6902,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = {
        .nr_functions = ARRAY_SIZE(pinmux_functions.common),
 
        .cfg_regs = pinmux_config_regs,
+       .bias_regs = pinmux_bias_regs,
 
        .pinmux_data = pinmux_data,
        .pinmux_data_size = ARRAY_SIZE(pinmux_data),
@@ -6677,7 +6912,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = {
 #ifdef CONFIG_PINCTRL_PFC_R8A7744
 const struct sh_pfc_soc_info r8a7744_pinmux_info = {
        .name = "r8a77440_pfc",
-       .ops = &r8a7791_pinmux_ops,
+       .ops = &r8a7791_pfc_ops,
        .unlock_reg = 0xe6060000, /* PMMR */
 
        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6690,6 +6925,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = {
        .nr_functions = ARRAY_SIZE(pinmux_functions.common),
 
        .cfg_regs = pinmux_config_regs,
+       .bias_regs = pinmux_bias_regs,
 
        .pinmux_data = pinmux_data,
        .pinmux_data_size = ARRAY_SIZE(pinmux_data),
@@ -6699,7 +6935,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = {
 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
        .name = "r8a77910_pfc",
-       .ops = &r8a7791_pinmux_ops,
+       .ops = &r8a7791_pfc_ops,
        .unlock_reg = 0xe6060000, /* PMMR */
 
        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6714,6 +6950,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = {
                        ARRAY_SIZE(pinmux_functions.automotive),
 
        .cfg_regs = pinmux_config_regs,
+       .bias_regs = pinmux_bias_regs,
 
        .pinmux_data = pinmux_data,
        .pinmux_data_size = ARRAY_SIZE(pinmux_data),
@@ -6723,7 +6960,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = {
 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
        .name = "r8a77930_pfc",
-       .ops = &r8a7791_pinmux_ops,
+       .ops = &r8a7791_pfc_ops,
        .unlock_reg = 0xe6060000, /* PMMR */
 
        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6738,6 +6975,7 @@ const struct sh_pfc_soc_info r8a7793_pinmux_info = {
                        ARRAY_SIZE(pinmux_functions.automotive),
 
        .cfg_regs = pinmux_config_regs,
+       .bias_regs = pinmux_bias_regs,
 
        .pinmux_data = pinmux_data,
        .pinmux_data_size = ARRAY_SIZE(pinmux_data),