clk: rzg2l: Ignore enable for core clocks

In the RZ/G2L family, core clocks are always on and can't be disabled.
However, drivers which are shared with other SoCs may call clk_enable()
or clk_enable_bulk() for a clock referenced in the device tree which
happens to be a core clock on the RZ/G2L. To avoid the need for
conditionals in these drivers, simply ignore attempts to enable a core
clock.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index c8735d869cf9380ca0f626d12ca63827ee39a23a..3c5340df8eed30028e45c231ff2879efd1c2634c 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -69,7 +69,15 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
 
        dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable",
                is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id);
+
        if (!is_mod_clk(clk->id)) {
+               /*
+                * Non-module clocks are always on. Ignore attempts to enable
+                * them and reject attempts to disable them.
+                */
+               if (enable)
+                       return 0;
+
                dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id);
                return -EINVAL;
        }