riscv: Update alignment for some sections in linker scripts

Some sections in the linker scripts are aligned to 4 bytes, which
may cause misaligned exception on some platforms, e.g.: clearing
the bss section on 64-bit hardware if __bss_start does not start
from a naturally 8 bytes aligned address.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index c3b490790560bfbb95960d72a5699af00863d1b3..d1113a59aa69f13a9d7932824a0bff2f489c553d 100644 (file)
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -44,7 +44,7 @@ SECTIONS
                __binman_sym_end = .;
        } > .spl_mem
 
-       . = ALIGN(4);
+       . = ALIGN(8);
 
        _end = .;
        _image_binary_end = .;

diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index 1c937aebee082ded60773250fe6a8a17bf39bf6e..15b5cbc585dba17088f1a8af188cbdef05091e20 100644 (file)
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -57,7 +57,7 @@ SECTIONS
                __efi_runtime_rel_stop = .;
        }
 
-       . = ALIGN(4);
+       . = ALIGN(8);
 
        /DISCARD/ : { *(.rela.plt*) }
        .rela.dyn : {
@@ -66,7 +66,7 @@ SECTIONS
                __rel_dyn_end = .;
        }
 
-       . = ALIGN(4);
+       . = ALIGN(8);
 
        .dynsym : {
                __dyn_sym_start = .;
@@ -74,7 +74,7 @@ SECTIONS
                __dyn_sym_end = .;
        }
 
-       . = ALIGN(4);
+       . = ALIGN(8);
 
        _end = .;