LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
+#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
#include <asm/fsl_i2c.h>
+#include "../common/pq-mds-pib.h"
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_PCI)
-#define PCI_FUNCTION_CONFIG 0x44
-#define PCI_FUNCTION_CFG_LOCK 0x20
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxemds_config_table[] = {
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
{
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_cfgfunc_config_device,
- {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
- {}
-}
-#endif
-static struct pci_controller hose[] = {
{
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxemds_config_table,
-#endif
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
},
};
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
-/**********************************************************************
- * pci_init_board()
- *********************************************************************/
void pci_init_board(void)
#ifdef CONFIG_PCISLAVE
{
- u16 reg16;
- volatile immap_t *immr;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+ struct pci_region *reg[] = { pci1_regions };
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+ mpc83xx_pci_init(1, reg, 0);
- immr = (immap_t *) CONFIG_SYS_IMMR;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
/*
* Configure PCI Inbound Translation Windows
*/
pci_ctrl[0].piebar2 = 0x0;
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
- pci_setup_indirect(&hose[0],
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
- reg16 = 0xff;
-
- pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
- PCI_LATENCY_TIMER, 0x80);
-
- /*
- * Unlock configuration lock in PCI function configuration register.
- */
- pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_FUNCTION_CONFIG, ®16);
- reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_FUNCTION_CONFIG, reg16);
-
- printf("Enabled PCI 32bit Agent Mode\n");
+ /* Unlock the configuration bit */
+ mpc83xx_pcislave_unlock(0);
+ printf("PCI: Agent mode enabled\n");
}
#else
{
- volatile immap_t *immr;
- volatile clk83xx_t *clk;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
- u16 reg16;
- u32 val32;
- u32 dev;
+ /* initialize the PCA9555PW IO expander on the PIB board */
+ pib_init();
- immr = (immap_t *) CONFIG_SYS_IMMR;
- clk = (clk83xx_t *) & immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
- val32 = clk->occr;
- udelay(2000);
#if defined(PCI_66M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
#endif
udelay(2000);
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI mem space - prefetch */
- pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr =
- POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI mmio - non-prefetch mem space */
- pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI IO space */
- pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
- pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 =
- PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
- PIWAR_IWS_2G;
-
- /*
- * Release PCI RST Output signal
- */
udelay(2000);
- pci_ctrl[0].gcr = 1;
- udelay(2000);
-
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose[0].regions + 0,
- CONFIG_SYS_PCI_MEM_BASE,
- CONFIG_SYS_PCI_MEM_PHYS,
- CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose[0].regions + 1,
- CONFIG_SYS_PCI_MMIO_BASE,
- CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose[0].regions + 2,
- CONFIG_SYS_PCI_IO_BASE,
- CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose[0].regions + 3,
- CONFIG_SYS_PCI_SLV_MEM_LOCAL,
- CONFIG_SYS_PCI_SLV_MEM_BUS,
- CONFIG_SYS_PCI_SLV_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
- hose[0].region_count = 4;
-
- pci_setup_indirect(&hose[0],
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(0, 0, 0);
- pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg, 0);
+#else
+ mpc83xx_pci_init(2, reg, 0);
+#endif
}
#endif /* CONFIG_PCISLAVE */
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(hose[0].first_busno);
- tmp[1] = cpu_to_be32(hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
- }
-}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_PCI
-
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
printf("PCI: Agent mode enabled\n");
}
#endif /* CONFIG_PCISLAVE */
-
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <common.h>
-#ifdef CONFIG_PCI
-
#include <asm/mmu.h>
-#include <asm/global_data.h>
+#include <asm/io.h>
+#include <mpc83xx.h>
#include <pci.h>
-#include <asm/mpc8349_pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
+#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8349itx_config_table[] = {
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
{
- PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_IDSEL_NUMBER,
- PCI_ANY_ID,
- pci_cfgfunc_config_device,
- {
- PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
- },
- {}
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
};
-#endif
-static struct pci_controller pci_hose[] = {
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
{
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349itx_config_table,
-#endif
- },
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
{
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349itx_config_table,
-#endif
- }
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
};
+#endif
-/**************************************************************************
- * pci_init_board()
- *
- * NOTICE: PCI2 is not currently supported
- *
- */
void pci_init_board(void)
{
- volatile immap_t *immr;
- volatile clk83xx_t *clk;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
u8 reg8;
- u16 reg16;
- u32 reg32;
- u32 dev;
- struct pci_controller *hose;
-
- immr = (immap_t *) CONFIG_SYS_IMMR;
- clk = (clk83xx_t *) & immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
-
- hose = &pci_hose[0];
-
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
-
- reg32 = clk->occr;
- udelay(2000);
#ifdef CONFIG_HARD_I2C
i2c_set_bus_num(1);
#else
clk->occr = 0xff000000; /* 66 MHz PCI */
#endif
-
- udelay(2000);
-
- /*
- * Release PCI RST Output signal
- */
- pci_ctrl[0].gcr = 0;
- udelay(2000);
- pci_ctrl[0].gcr = 1;
-
-#ifdef CONFIG_MPC83XX_PCI2
- pci_ctrl[1].gcr = 0;
udelay(2000);
- pci_ctrl[1].gcr = 1;
-#endif
-
- /* We need to wait at least a 1sec based on PCI specs */
- {
- int i;
- for (i = 0; i < 1000; i++)
- udelay(1000);
- }
-
- /*
- * Configure PCI Local Access Windows
- */
+ /* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI1 mem space - prefetch */
- pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
-
- /* PCI1 IO space */
- pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
-
- /* PCI1 mmio - non-prefetch mem space */
- pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_MMIO_BASE,
- CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 4;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-
-#ifdef CONFIG_MPC83XX_PCI2
- hose = &pci_hose[1];
-
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI2 mem space - prefetch */
- pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
-
- /* PCI2 IO space */
- pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
-
- /* PCI2 mmio - non-prefetch mem space */
- pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[1].pitar1 = 0x0;
- pci_ctrl[1].pibar1 = 0x0;
- pci_ctrl[1].piebar1 = 0x0;
- pci_ctrl[1].piwar1 =
- PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
- (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = pci_hose[0].last_busno + 1;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI2_MEM_BASE,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI2_MMIO_BASE,
- CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI2_IO_BASE,
- CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 4;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR + 0x8380), (CONFIG_SYS_IMMR + 0x8384));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#ifdef CONFIG_MPC83XX_PCI2
- path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
+ udelay(2000);
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg, 0);
+#else
+ mpc83xx_pci_init(2, reg, 0);
#endif
- }
}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
/*
* PCI Configuration space access support for MPC83xx PCI Bridge
*/
+
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
+#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
#include <asm/fsl_i2c.h>
+#include "../common/pq-mds-pib.h"
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_PCI)
-#define PCI_FUNCTION_CONFIG 0x44
-#define PCI_FUNCTION_CFG_LOCK 0x20
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxemds_config_table[] = {
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
{
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_cfgfunc_config_device,
- {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
- },
- {}
-}
-#endif
-static struct pci_controller hose[] = {
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
{
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxemds_config_table,
-#endif
- },
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
};
+#endif
-/**********************************************************************
- * pci_init_board()
- *********************************************************************/
void pci_init_board(void)
#ifdef CONFIG_PCISLAVE
{
- u16 reg16;
- volatile immap_t *immr;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+ struct pci_region *reg[] = { pci1_regions };
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+ mpc83xx_pci_init(1, reg, 0);
- immr = (immap_t *) CONFIG_SYS_IMMR;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
/*
* Configure PCI Inbound Translation Windows
*/
pci_ctrl[0].piebar2 = 0x0;
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
- pci_setup_indirect(&hose[0],
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
- reg16 = 0xff;
-
- pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
- PCI_LATENCY_TIMER, 0x80);
-
- /*
- * Unlock configuration lock in PCI function configuration register.
- */
- pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_FUNCTION_CONFIG, ®16);
- reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
- pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
- PCI_FUNCTION_CONFIG, reg16);
-
- printf("Enabled PCI 32bit Agent Mode\n");
+ /* Unlock the configuration bit */
+ mpc83xx_pcislave_unlock(0);
+ printf("PCI: Agent mode enabled\n");
}
#else
{
- volatile immap_t *immr;
- volatile clk83xx_t *clk;
- volatile law83xx_t *pci_law;
- volatile pot83xx_t *pci_pot;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile pciconf83xx_t *pci_conf;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
- u16 reg16;
- u32 val32;
- u32 dev;
+ /* initialize the PCA9555PW IO expander on the PIB board */
+ pib_init();
- immr = (immap_t *) CONFIG_SYS_IMMR;
- clk = (clk83xx_t *) & immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
- val32 = clk->occr;
- udelay(2000);
#if defined(PCI_66M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
#endif
udelay(2000);
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI mem space - prefetch */
- pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr =
- POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI mmio - non-prefetch mem space */
- pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI IO space */
- pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
- pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 =
- PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
- PIWAR_IWS_2G;
-
- /*
- * Release PCI RST Output signal
- */
- udelay(2000);
- pci_ctrl[0].gcr = 1;
udelay(2000);
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose[0].regions + 0,
- CONFIG_SYS_PCI_MEM_BASE,
- CONFIG_SYS_PCI_MEM_PHYS,
- CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose[0].regions + 1,
- CONFIG_SYS_PCI_MMIO_BASE,
- CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose[0].regions + 2,
- CONFIG_SYS_PCI_IO_BASE,
- CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose[0].regions + 3,
- CONFIG_SYS_PCI_SLV_MEM_LOCAL,
- CONFIG_SYS_PCI_SLV_MEM_BUS,
- CONFIG_SYS_PCI_SLV_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose[0].region_count = 4;
-
- pci_setup_indirect(&hose[0],
- (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(0, 0, 0);
- pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg, 0);
+#else
+ mpc83xx_pci_init(2, reg, 0);
+#endif
}
#endif /* CONFIG_PCISLAVE */
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(hose[0].first_busno);
- tmp[1] = cpu_to_be32(hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
- }
-}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <asm/fsl_i2c.h>
#include <asm/fsl_serdes.h>
-#if defined(CONFIG_PCI)
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI_MEM_BASE,
do_fixup_by_path(blob, "pci2", "status", status,
strlen(status) + 1, 1);
}
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <pci.h>
#include <asm/io.h>
-#if defined(CONFIG_PCI)
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI_MEM_BASE,
mpc83xx_pcie_init(2, pcie_reg, 0);
}
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
* pci.c -- WindRiver SBC8349 PCI board support.
* Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Based on MPC8349 PCI support but w/o PIB related code.
*
*/
#include <asm/mmu.h>
+#include <asm/io.h>
#include <common.h>
-#include <asm/global_data.h>
+#include <mpc83xx.h>
#include <pci.h>
-#include <asm/mpc8349_pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
+#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_PCI
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8349emds_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- }
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
},
- {}
-};
-#endif
-
-static struct pci_controller pci_hose[] = {
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- },
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- }
};
-/**************************************************************************
+/*
* pci_init_board()
*
* NOTICE: PCI2 is not supported. There is only one
void
pci_init_board(void)
{
- volatile immap_t * immr;
- volatile clk83xx_t * clk;
- volatile law83xx_t * pci_law;
- volatile pot83xx_t * pci_pot;
- volatile pcictrl83xx_t * pci_ctrl;
- volatile pciconf83xx_t * pci_conf;
- u16 reg16;
- u32 reg32;
- u32 dev;
- struct pci_controller * hose;
-
- immr = (immap_t *)CONFIG_SYS_IMMR;
- clk = (clk83xx_t *)&immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
-
- hose = &pci_hose[0];
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci1_regions };
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
-
- reg32 = clk->occr;
- udelay(2000);
+ /* Enable all 8 PCI_CLK_OUTPUTS */
clk->occr = 0xff000000;
udelay(2000);
- /*
- * Release PCI RST Output signal
- */
- pci_ctrl[0].gcr = 0;
- udelay(2000);
- pci_ctrl[0].gcr = 1;
-
-#ifdef CONFIG_MPC83XX_PCI2
- pci_ctrl[1].gcr = 0;
- udelay(2000);
- pci_ctrl[1].gcr = 1;
-#endif
-
- /* We need to wait at least a 1sec based on PCI specs */
- {
- int i;
-
- for (i = 0; i < 1000; ++i)
- udelay (1000);
- }
-
- /*
- * Configure PCI Local Access Windows
- */
+ /* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI1 mem space - prefetch */
- pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI1 IO space */
- pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /* PCI1 mmio - non-prefetch mem space */
- pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM|PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_MMIO_BASE,
- CONFIG_SYS_PCI1_MMIO_PHYS,
- CONFIG_SYS_PCI1_MMIO_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 4;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x8300),
- (CONFIG_SYS_IMMR+0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-
-#ifdef CONFIG_MPC83XX_PCI2
- hose = &pci_hose[1];
-
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI2 mem space - prefetch */
- pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /* PCI2 IO space */
- pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-
- /* PCI2 mmio - non-prefetch mem space */
- pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[1].pitar1 = 0x0;
- pci_ctrl[1].pibar1 = 0x0;
- pci_ctrl[1].piebar1 = 0x0;
- pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
-
- hose->first_busno = pci_hose[0].last_busno + 1;
- hose->last_busno = 0xff;
-
- /* PCI memory prefetch space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI2_MEM_BASE,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE,
- PCI_REGION_MEM|PCI_REGION_PREFETCH);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI2_MMIO_BASE,
- CONFIG_SYS_PCI2_MMIO_PHYS,
- CONFIG_SYS_PCI2_MMIO_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI2_IO_BASE,
- CONFIG_SYS_PCI2_IO_PHYS,
- CONFIG_SYS_PCI2_IO_SIZE,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 3,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 4;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x8380),
- (CONFIG_SYS_IMMR+0x8384));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-#endif
-
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#ifdef CONFIG_MPC83XX_PCI2
- path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
+ udelay(2000);
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#endif
- }
+ mpc83xx_pci_init(1, reg, 0);
}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <asm/mmu.h>
+#include <asm/io.h>
#include <common.h>
-#include <asm/global_data.h>
+#include <mpc83xx.h>
#include <pci.h>
-#include <asm/mpc8349_pci.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_PCI
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_tqm834x_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- }
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
},
- {}
-};
-#endif
-
-static struct pci_controller pci1_hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_tqm834x_config_table,
-#endif
};
-
-/**************************************************************************
+/*
* pci_init_board()
*
* NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
void
pci_init_board(void)
{
- volatile immap_t * immr;
- volatile clk83xx_t * clk;
- volatile law83xx_t * pci_law;
- volatile pot83xx_t * pci_pot;
- volatile pcictrl83xx_t * pci_ctrl;
- volatile pciconf83xx_t * pci_conf;
- u16 reg16;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci1_regions };
u32 reg32;
- struct pci_controller * hose;
-
- immr = (immap_t *)CONFIG_SYS_IMMR;
- clk = (clk83xx_t *)&immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
-
- hose = &pci1_hose;
/*
* Configure PCI controller and PCI_CLK_OUTPUT
- */
-
- /*
+ *
* WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
* line actually used for clocking all external PCI devices in TQM83xx.
* Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
clk->occr = reg32;
udelay(2000);
- /*
- * Release PCI RST Output signal
- */
- pci_ctrl[0].gcr = 0;
- udelay(2000);
- pci_ctrl[0].gcr = 1;
- udelay(2000);
-
- /*
- * Configure PCI Local Access Windows
- */
+ /* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
- /*
- * Configure PCI Outbound Translation Windows
- */
-
- /* PCI1 mem space */
- pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
-
- /* PCI1 IO space */
- pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
-
- /* we need RAM mapped to PCI space for the devices to
- * access main memory */
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* PCI memory space */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(hose->regions + 2,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- CONFIG_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 3;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x8300),
- (CONFIG_SYS_IMMR+0x8304));
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
- ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
- reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
- 0xffff);
- pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
- 0x80);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- int nodeoffset;
- int tmp[2];
- const char *path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci1_hose.first_busno);
- tmp[1] = cpu_to_be32(pci1_hose.last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#ifdef CONFIG_MPC83XX_PCI2
- path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
- if (path) {
- tmp[0] = cpu_to_be32(pci2_hose.first_busno);
- tmp[1] = cpu_to_be32(pci2_hose.last_busno);
- do_fixup_by_path(blob, path, "bus-range",
- &tmp, sizeof(tmp), 1);
+ udelay(2000);
- tmp[0] = cpu_to_be32(gd->pci_clk);
- do_fixup_by_path(blob, path, "clock-frequency",
- &tmp, sizeof(tmp[0]), 1);
- }
-#endif
- }
+ mpc83xx_pci_init(1, reg, 0);
}
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_GENERIC_PCI
+#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
/*
* Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
+ */ #define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_GENERIC_PCI
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR 0x00000000
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_GENERIC_PCI
+#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* PCI1 host bridge */
-#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L (0)
#define CONFIG_SYS_IBAT3U (0)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_GENERIC_PCI
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
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