#include <asm/arch/dram_sun8i_a33.h>
#elif defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/dram_sun8i_a83t.h>
-#elif defined(CONFIG_MACH_SUNXI_H3_H5) || \
- defined(CONFIG_MACH_SUN8I_R40) || \
- defined(CONFIG_MACH_SUN50I)
-#include <asm/arch/dram_sun8i_h3.h>
+#elif defined(CONFIG_SUNXI_DRAM_DW)
+#include <asm/arch/dram_sunxi_dw.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/dram_sun9i.h>
#else
separate ahb reset control registers, custom pmic bus, new style
watchdog, etc.
+config SUNXI_DRAM_DW
+ bool
+ ---help---
+ Select this for sunxi SoCs which uses a DRAM controller like the
+ DesignWare controller used in H3, mainly SoCs after H3, which do
+ not have official open-source DRAM initialization code, but can
+ use modified H3 DRAM initialization code.
config MACH_SUNXI_H3_H5
bool
select DM_I2C
select SUNXI_DE2
+ select SUNXI_DRAM_DW
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SUNXI_DRAM_DW
config MACH_SUN8I_V3S
bool "sun8i (Allwinner V3s)"
select SUNXI_GEN_SUN6I
select SUNXI_HIGH_SRAM
select SUPPORT_SPL
+ select SUNXI_DRAM_DW
select FIT
select SPL_LOAD_FIT
obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
-obj-$(CONFIG_MACH_SUNXI_H3_H5) += dram_sun8i_h3.o
-obj-$(CONFIG_MACH_SUN8I_R40) += dram_sun8i_h3.o
+obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o
obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o
-obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o
endif