ns16550: unify serial_rockchip

Unify serial_rockchip, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 0f497099679470ea39078d6ca9e5b1ae550995b0..ac367f85b98807a7d5432ddadd81f1d9618ad73d 100644 (file)
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -324,6 +324,7 @@
                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
@@ -337,6 +338,7 @@
                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
@@ -350,6 +352,7 @@
                interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
@@ -362,6 +365,7 @@
                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
@@ -375,6 +379,7 @@
                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ab50f4e1f8a0c851a4d39f13093d7152818200e6..3f7dc8e19bd333ac57223dc1a4c16d2dc324f634 100644 (file)
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -33,9 +33,6 @@ config DM_I2C
 config DM_GPIO
        default y
 
-config ROCKCHIP_SERIAL
-       default y
-
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
 
 endif

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b41f508eb8c91eb59dc2356e067ee0568b1ba918..123941612822bd881d542e66659f3e03c2497b08 100644 (file)
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -186,19 +186,10 @@ config ALTERA_UART
          Select this to enable an UART for Altera devices. Please find
          details on the "Embedded Peripherals IP User Guide" of Altera.
 
-config ROCKCHIP_SERIAL
-       bool "Rockchip on-chip UART support"
-       depends on ARCH_ROCKCHIP && DM_SERIAL
-       help
-         Select this to enable a debug UART for Rockchip devices. This uses
-         the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
-         your board config header. The clock input is automatically set to
-         use the oscillator (24MHz).
-
 config NS16550_SERIAL
        bool "NS16550 UART or compatible"
        depends on DM_SERIAL
-       default y if X86 || PPC
+       default y if X86 || PPC || ARCH_ROCKCHIP
        help
          Support NS16550 UART or compatible with driver model. This can be
          enabled in the device tree with the correct input clock frequency.

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 9f61113fa7892b6da776d931fcb43452a4820bb3..debc175f5fcd4cafbccefee531f9084a45d0e8b3 100644 (file)
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -40,7 +40,6 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
 obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_MXS_AUART) += mxs_auart.o
-obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o

diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
deleted file mode 100644 (file)
index 0e7bbfc..0000000
--- a/drivers/serial/serial_rockchip.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-#include <asm/arch/clock.h>
-
-static const struct udevice_id rockchip_serial_ids[] = {
-       { .compatible = "rockchip,rk3288-uart" },
-       { }
-};
-
-static int rockchip_serial_ofdata_to_platdata(struct udevice *dev)
-{
-       struct ns16550_platdata *plat = dev_get_platdata(dev);
-       int ret;
-
-       ret = ns16550_serial_ofdata_to_platdata(dev);
-       if (ret)
-               return ret;
-
-       /* Do all Rockchip parts use 24MHz? */
-       plat->clock = 24 * 1000000;
-
-       return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
-       .name   = "serial_rockchip",
-       .id     = UCLASS_SERIAL,
-       .of_match = rockchip_serial_ids,
-       .ofdata_to_platdata = rockchip_serial_ofdata_to_platdata,
-       .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-       .priv_auto_alloc_size = sizeof(struct NS16550),
-       .probe = ns16550_serial_probe,
-       .ops    = &ns16550_serial_ops,
-       .flags  = DM_FLAG_PRE_RELOC,
-};