edminiv2: switch to SPL

ED Mini V2 is based on Orion 5x which boots at fixed
address 0xFFFF0000 in NOR Flash. Place SPL there, and
switch U-Boot from .bin to .img format, stored in
NOR Flash at 0xFFF90000.

Note: this patch was tested on HW and works, i.e.
it boots U-Boot properly, but SPL console output
currently does not appear, due to GD being trashed
by arch/arm/lib/spl.c. This trashing is soon to be
removed, and then ED Mini V2 SPL console output will
become visible.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>

diff --git a/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
new file mode 100644 (file)
index 0000000..6f7fca0
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on:
+ *
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Based on omap-common/u-boot-spl.lds:
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *     Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+               LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+               LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       .text      :
+       {
+               __start = .;
+               *(.vectors)
+               CPUDIR/start.o  (.text)
+               *(.text*)
+       } > .nor
+
+       . = ALIGN(4);
+       .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
+
+       . = ALIGN(4);
+       .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
+
+       . = ALIGN(4);
+       .u_boot_list : {
+               KEEP(*(SORT(.u_boot_list*)));
+       } > .nor
+
+       . = ALIGN(4);
+       __image_copy_end = .;
+       _end = .;
+
+       .bss :
+       {
+               . = ALIGN(4);
+               __bss_start = .;
+               *(.bss*)
+               . = ALIGN(4);
+               __bss_end = .;
+       } > .bss
+}

diff --git a/arch/arm/include/asm/arch-orion5x/spl.h b/arch/arm/include/asm/arch-orion5x/spl.h
new file mode 100644 (file)
index 0000000..23745bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/spl.h
@@ -0,0 +1,10 @@
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef        _ASM_ARCH_SPL_H_
+#define        _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NOR                1

diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 5a542629c75e107c4116a301e569e983175c2841..291c511ba85e7794c4ee4a4d2ad7722b560c3aa1 100644 (file)
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -5,6 +5,7 @@ choice
 
 config TARGET_EDMINIV2
        bool "LaCie Ethernet Disk mini V2"
+       select SUPPORT_SPL
 
 endchoice
 

diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c
index f88db3b1f96ad400fdf47c0e3bbd83f91a46ed6a..2ecd3856780cb10533a9d1981eb97f14a23188a7 100644 (file)
--- a/arch/arm/mach-orion5x/cpu.c
+++ b/arch/arm/mach-orion5x/cpu.c
@@ -234,7 +234,9 @@ int arch_cpu_init(void)
        /* Enable and invalidate L2 cache in write through mode */
        invalidate_l2_cache();
 
+#ifdef CONFIG_SPL_BUILD
        orion5x_config_adr_windows();
+#endif
 
        return 0;
 }

diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S
index 4dacc296e41aa3dea563c92fd385f64b35d26424..51a8b3c51b2fedb18e836794d6931a0d0508c751 100644 (file)
--- a/arch/arm/mach-orion5x/lowlevel_init.S
+++ b/arch/arm/mach-orion5x/lowlevel_init.S
@@ -62,14 +62,16 @@
 /*
  * Low-level init happens right after start.S has switched to SVC32,
  * flushed and disabled caches and disabled MMU. We're still running
- * from the boot chip select, so the first thing we should do is set
- * up RAM for us to relocate into.
+ * from the boot chip select, so the first thing SPL should do is to
+ * set up the RAM to copy U-Boot into.
  */
 
 .globl lowlevel_init
 
 lowlevel_init:
 
+#ifdef CONFIG_SPL_BUILD
+
        /* Use 'r4 as the base for internal register accesses */
        ldr     r4, =ORION5X_REGS_PHY_BASE
 
@@ -273,5 +275,13 @@ lowlevel_init:
        orr     r2, r2, r6
        str     r2, [r3, #0x484]
 
+       /* enable for 2 GB DDR; detection should find out real amount */
+       sub     r6, r6, r6
+       str     r6, [r3, #0x500]
+       ldr     r6, =0x7fff0001
+       str     r6, [r3, #0x504]
+
+#endif /* CONFIG_SPL_BUILD */
+
        /* Return to U-boot via saved link register */
        mov     pc, lr

diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index 80ec7faa049476ee7c57a98471fcd34e2e92c934..2983201801746087813c183a5bb1fdea5dbaf891 100644 (file)
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -12,6 +12,8 @@
 #include <miiphy.h>
 #include <asm/arch/orion5x.h>
 #include "../common/common.h"
+#include <spl.h>
+#include <ns16550.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -83,3 +85,21 @@ void reset_phy(void)
        mv_phy_88e1116_init("egiga0", 8);
 }
 #endif /* CONFIG_RESET_PHY_R */
+
+/*
+ * SPL serial setup and NOR boot device selection
+ */
+
+#ifdef CONFIG_SPL_BUILD
+
+void spl_board_init(void)
+{
+       preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+       return BOOT_DEVICE_NOR;
+}
+
+#endif /* CONFIG_SPL_BUILD */

diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index 3b1a6c193a703521a9a549567d99541471a26aab..20c1c65e1ff91633a58dc6f82f40d97a0f9612c9 100644 (file)
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -1,3 +1,4 @@
-CONFIG_ARM=y
-CONFIG_ORION5X=y
-CONFIG_TARGET_EDMINIV2=y
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ORION5X=y
++S:CONFIG_TARGET_EDMINIV2=y

diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 47da4a919526e172a45891b1bac4cdf62dbc0876..ee5f76b9ec567f75e9c4cad501e4e704019c10a6 100644 (file)
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -13,9 +13,30 @@
 #define _CONFIG_EDMINIV2_H
 
 /* general settings */
-#define CONFIG_SYS_TEXT_BASE 0xfff90000
 #define CONFIG_SYS_GENERIC_BOARD
 
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NOR_SUPPORT
+#define CONFIG_SPL_TEXT_BASE           0xffff0000
+#define CONFIG_SPL_MAX_SIZE            0x0000fff0
+#define CONFIG_SPL_STACK               0x00020000
+#define CONFIG_SPL_BSS_START_ADDR      0x00020000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x0001ffff
+#define CONFIG_SYS_SPL_MALLOC_START    0x00040000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x0001ffff
+#define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/orion5x/u-boot-spl.lds"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_UBOOT_BASE          0xfff90000
+#define CONFIG_SYS_UBOOT_START         0x00800000
+#define CONFIG_SYS_TEXT_BASE           0x00800000
+
 /*
  * Version number information
  */