U_BOOT_DRIVER(syscon_rk3399) = {
.name = "rk3399_syscon",
.id = UCLASS_SYSCON,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.of_match = rk3399_syscon_ids,
.name = "rk3568_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3568_syscon_ids,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
};
ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
if (ret)
return log_msg_ret("no hostbridge PINCTRL", ret);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int root;
/* Get length of PCI Express Region */
#endif
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_hostbridge_ids[] = {
{ .compatible = "intel,apl-hostbridge" },
{ }
.inject_dsdt = southbridge_inject_dsdt,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_lpc_ids[] = {
{ .compatible = "intel,apl-lpc" },
{ }
.set_spi_protect = apl_set_spi_protect,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_pch_ids[] = {
{ .compatible = "intel,apl-pch" },
{ }
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
struct apl_pmc_plat *plat = dev_get_plat(dev);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
u32 base[6];
int size;
int ret;
.global_reset_set_enable = apl_global_reset_set_enable,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_pmc_ids[] = {
{ .compatible = "intel,apl-pmc" },
{ }
return 0;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_ns16550_serial_ids[] = {
{ .compatible = "intel,apl-ns16550" },
{ },
#endif
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id itss_ids[] = {
{ .compatible = "intel,itss", .data = X86_IRQT_ITSS },
{ }
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
struct p2sb_plat *plat = dev_get_plat(dev);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int ret;
u32 base[2];
static int p2sb_child_post_bind(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
.set_hide = intel_p2sb_set_hide,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id p2sb_ids[] = {
{ .compatible = "intel,p2sb" },
{ }
* for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
* the auto allocation (after relocation).
*/
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id tpl_fake_pci_ids[] = {
{ .compatible = "pci-x86" },
{ }
.get_str = coral_get_str,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id coral_ids[] = {
{ .compatible = "google,coral" },
{ }
gd_t *gd;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-/* Add a simple GPIO device */
+/*
+ * Add a simple GPIO device (don't use with of-platdata as it interferes with
+ * the auto-generated devices)
+ */
U_BOOT_DRVINFO(gpio_sandbox) = {
.name = "sandbox_gpio",
};
static int mmc_of_to_plat(struct udevice *dev)
{
- #if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ #if CONFIG_IS_ENABLED(OF_REAL)
/* Decode the devicetree data */
struct mmc_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
static int clk_fixed_factor_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int err;
struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
struct clk_fixed_rate *plat)
{
struct clk *clk = &plat->clk;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", 0);
#endif
/* Make fixed rate clock accessible from higher level struct clk */
static int rk3188_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3188_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
static int rk3288_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3288_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
static int rk3368_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3368_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
static int rk3399_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3399_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
priv->pmucru = dev_read_addr_ptr(dev);
.per_device_plat_auto = sizeof(struct simple_bus_plat),
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id generic_simple_bus_ids[] = {
{ .compatible = "simple-bus" },
{ .compatible = "simple-mfd" },
U_BOOT_DRIVER(generic_syscon) = {
.name = "syscon",
.id = UCLASS_SYSCON,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.of_match = generic_syscon_ids,
return count;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
int pci_get_devfn(struct udevice *dev)
{
struct fdt_pci_addr addr;
return ret;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int _gpio_request_by_name_nodev(ofnode node, const char *list_name,
int index, struct gpio_desc *desc,
int flags, bool add_index)
#endif
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id intel_intel_gpio_ids[] = {
{ .compatible = "intel,gpio" },
{ }
.name = "gpio_omap",
.id = UCLASS_GPIO,
#if CONFIG_IS_ENABLED(OF_CONTROL)
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = omap_gpio_ids,
.of_to_plat = of_match_ptr(omap_gpio_of_to_plat),
.plat_auto = sizeof(struct omap_gpio_plat),
UCLASS_DRIVER(i2c_emul_parent) = {
.id = UCLASS_I2C_EMUL_PARENT,
.name = "i2c_emul_parent",
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
};
.id = UCLASS_CROS_EC,
.name = "cros-ec",
.per_device_auto = sizeof(struct cros_ec_dev),
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
.flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
static int p2sb_child_post_bind(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
static int fsl_esdhc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
return ret;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct ftsdc_priv *priv = dev_get_priv(dev);
struct ftsdc010_chip *chip = &priv->chip;
chip->name = dev->name;
static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
return intel_pinctrl_of_to_plat(dev, comm, 2);
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id apl_gpio_ids[] = {
{ .compatible = "intel,apl-pinctrl"},
{ }
.of_match = of_match_ptr(apl_gpio_ids),
.probe = intel_pinctrl_probe,
.ops = &intel_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.of_to_plat = apl_pinctrl_of_to_plat,
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(mxs_pinctrl_match),
.probe = mxs_pinctrl_probe,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.priv_auto = sizeof(struct mxs_pinctrl_priv),
UCLASS_DRIVER(pinctrl) = {
.id = UCLASS_PINCTRL,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = pinctrl_post_bind,
#endif
.flags = DM_UC_FLAG_SEQ_ALIAS,
.of_match = px30_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3036_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3128_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3188_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3228_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3288_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3308_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3328_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3368_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rk3399_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
.of_match = rv1108_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.probe = rockchip_pinctrl_probe,
{
int ret = 0;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3368_sdram_params *plat = dev_get_plat(dev);
ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
static int rk3188_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3188_sdram_params *params = dev_get_plat(dev);
int ret;
static int rk322x_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk322x_sdram_params *params = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
static int rk3288_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3288_sdram_params *params = dev_get_plat(dev);
int ret;
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3328_sdram_params *params = &plat->sdram_params;
#else
struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
static int rk3328_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
static int rk3399_dmc_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
struct dram_info *priv = dev_get_priv(dev);
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3399_sdram_params *params = &plat->sdram_params;
#else
struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
.name = "rtc",
.id = UCLASS_RTC,
.flags = DM_UC_FLAG_SEQ_ALIAS,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.post_bind = dm_scan_fdt_dev,
#endif
};
.flags = DM_FLAG_PRE_RELOC,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct sandbox_serial_plat platdata_non_fdt = {
.colour = -1,
};
return 0;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int mt7620_serial_of_to_plat(struct udevice *dev)
{
struct mt7620_serial_plat *plat = dev_get_plat(dev);
U_BOOT_DRIVER(serial_mt7620) = {
.name = "serial_mt7620",
.id = UCLASS_SERIAL,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = mt7620_serial_ids,
.of_to_plat = mt7620_serial_of_to_plat,
#endif
return ret;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
/**
* ich_spi_get_basics() - Get basic information about the ICH device
*
uint *map_sizep, uint *offsetp)
{
pci_dev_t spi_bdf;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
if (device_is_on_pci_bus(bus)) {
struct pci_child_plat *pplat;
{
struct ich_spi_plat *plat = dev_get_plat(dev);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct ich_spi_priv *priv = dev_get_priv(dev);
int ret;
.cs_info = pl022_cs_info,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int pl022_spi_of_to_plat(struct udevice *bus)
{
struct pl022_spi_pdata *plat = dev_get_plat(bus);
U_BOOT_DRIVER(pl022_spi) = {
.name = "pl022_spi",
.id = UCLASS_SPI,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.of_match = pl022_spi_ids,
.of_to_plat = pl022_spi_of_to_plat,
#endif
static int rockchip_spi_of_to_plat(struct udevice *bus)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
return ret;
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static int spi_child_post_bind(struct udevice *dev)
{
struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
static int spi_post_probe(struct udevice *bus)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
.per_device_auto = sizeof(struct dm_spi_bus),
.per_child_auto = sizeof(struct spi_slave),
.per_child_plat_auto = sizeof(struct dm_spi_slave_plat),
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
.child_post_bind = spi_child_post_bind,
#endif
};
.ops = &sandbox_warm_sysreset_ops,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
/* This is here in case we don't have a device tree */
U_BOOT_DRVINFO(sysreset_sandbox_non_fdt) = {
.name = "sysreset_sandbox",
/* The timer is available */
rate = timer_get_rate(gd->timer);
timer_get_count(gd->timer, &ticks);
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
} else if (ret == -EAGAIN) {
/* We have been called so early that the DM is not ready,... */
ofnode node = offset_to_ofnode(-1);
static int rockchip_clk_of_to_plat(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_timer_priv *priv = dev_get_priv(dev);
priv->timer = dev_read_addr_ptr(dev);
static int timer_pre_probe(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk timer_clk;
int err;
if (gd->dm_root == NULL)
return -EAGAIN;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
/* Check for a chosen timer to be used for tick */
node = ofnode_get_chosen_node("tick-timer");
.get_count = tsc_timer_get_count,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
static const struct udevice_id tsc_timer_ids[] = {
{ .compatible = "x86,tsc-timer", },
{ }
u32 flags_;
#endif
int seq_;
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
ofnode node_;
#endif
#ifdef CONFIG_DEVRES
*/
static inline ofnode dev_ofnode(const struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
return dev->node_;
#else
return ofnode_null();
static inline int dev_of_offset(const struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
return ofnode_to_offset(dev_ofnode(dev));
#else
return -1;
static inline bool dev_has_ofnode(const struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
return ofnode_valid(dev_ofnode(dev));
#else
return false;
static inline void dev_set_ofnode(struct udevice *dev, ofnode node)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_REAL)
dev->node_ = node;
#endif
}