obj-y += cpu_init.o
obj-y += speed.o
obj-y += interrupts.o
-obj-y += ecc.o
+obj-$(CONFIG_DDR_ECC_CMD) += ecc.o
ifndef CONFIG_PINCTRL
obj-$(CONFIG_QE) += qe_io.o
endif
#include <mpc83xx.h>
#include <command.h>
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
void ecc_print_status(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
" - writes pattern injecting errors with word access\n"
" - writes pattern with word access, generates error\n"
" - disables injects\n" " - re-inits memory");
-#endif
#endif
#endif
-/* Check if boards need to enable FSL DMA engine for SDRAM init */
-#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
-#if ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
-#define CONFIG_FSL_DMA
-#endif
-#endif
-
/*
* Provide a default boot page translation virtual address that lines up with
* Freescale's default e500 reset page.
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_DM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_DM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_DM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEC0C0000
CONFIG_DDR_CLK_FREQ=66666666
+# CONFIG_DDR_SPD is not set
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+# CONFIG_DDR_SPD is not set
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
+# CONFIG_DDR_SPD is not set
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_ENV_ADDR=0x60500000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_DM=y
CONFIG_SPL_DM=y
# CONFIG_SPL_BLK is not set
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_SPL_DM=y
CONFIG_SCSI_AHCI=y
# CONFIG_SPL_BLK is not set
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
help
Select Freescale Multi Mode DDR controller (MMDC).
+if SYS_FSL_DDR || SYS_FSL_MMDC
+
config SYS_FSL_DDR_BE
bool
help
endmenu
+config FSL_DMA
+ def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
+
+config DDR_ECC
+ bool "ECC DDR memory support"
+
+config DDR_ECC_CMD
+ bool "Access the ECC features of the memory controller"
+ depends on DDR_ECC && MPC83xx
+ default y
+
+config ECC_INIT_VIA_DDRCONTROLLER
+ bool "DDR Memory controller initializes memory."
+ help
+ Use the DDR controller to auto initialize memory. If not enabled,
+ the DMA controller is responsible for doing this.
+
+endif
+
config SYS_FSL_ERRATUM_A008378
bool
/*
* DDR Setup
*/
-#define CONFIG_DDR_ECC /* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
#define SPD_EEPROM_ADDRESS2 0x51
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
/*
* DDR Setup
*/
-#define CONFIG_DDR_ECC /* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
#define SPD_EEPROM_ADDRESS2 0x51
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
-#undef CONFIG_DDR_ECC /* support DDR ECC function */
-#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
-
#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
/*
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#endif
#endif /* CONFIG_RAMBOOT_PBL */
-#define CONFIG_DDR_ECC
-
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
-
/*
* IFC Definitions
*/
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define CONFIG_KSNET_CPSW_NUM_PORTS 9
#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
-#define CONFIG_DDR_SPD
-
#endif /* __CONFIG_K2E_EVM_H */
#define CONFIG_KSNET_NETCP_V1_0
#define CONFIG_KSNET_CPSW_NUM_PORTS 5
-#define CONFIG_DDR_SPD
-
#endif /* __CONFIG_K2HK_EVM_H */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#endif
/* DDR */
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_MONITOR_LEN 0x80000
#endif
-#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifndef CONFIG_SPL
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#ifdef CONFIG_SD_BOOT
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-#define CONFIG_DDR_SPD
#ifdef CONFIG_EMU
#define CONFIG_SYS_FSL_DDR_EMU
#else
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000