x86: Update device tree for TPL

Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 1050236330a5630b8dd6b78cde6ed28d729343f0..9cf733806a5204cc42edf0edb8d5ab633e92e68e 100644 (file)
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -22,7 +22,21 @@
                        filename = CONFIG_INTEL_ME_FILE;
                };
 #endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+               u-boot-tpl-with-ucode-ptr {
+                       offset = <CONFIG_TPL_TEXT_BASE>;
+               };
+               u-boot-tpl-dtb {
+               };
+               u-boot-spl {
+                       offset = <CONFIG_SPL_TEXT_BASE>;
+               };
+               u-boot-spl-dtb {
+               };
+               u-boot {
+                       offset = <CONFIG_SYS_TEXT_BASE>;
+               };
+#elif defined(CONFIG_SPL)
                u-boot-spl-with-ucode-ptr {
                        offset = <CONFIG_SPL_TEXT_BASE>;
                };
@@ -31,7 +45,19 @@
                        type = "u-boot-dtb-with-ucode";
                };
                u-boot {
+               /*
+                * TODO(sjg@chromium.org):
+                * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
+                * for boards with textbase in SDRAM we cannot do this. Just use
+                * an assumed-valid value (1MB before the end of flash) here so
+                * that we can actually build an image for coreboot, etc.
+                * We need a better solution, perhaps a separate Kconfig.
+                */
+#if CONFIG_SYS_TEXT_BASE == 0x1110000
                        offset = <0xfff00000>;
+#else
+                       offset = <CONFIG_SYS_TEXT_BASE>;
+#endif
                };
 #else
                u-boot-with-ucode-ptr {
@@ -77,7 +103,11 @@
                        offset = <CONFIG_X86_REFCODE_ADDR>;
                };
 #endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+               x86-start16-tpl {
+                       offset = <CONFIG_SYS_X86_START16>;
+               };
+#elif defined(CONFIG_SPL)
                x86-start16-spl {
                        offset = <CONFIG_SYS_X86_START16>;
                };