board: st: create common file stpmic1.c

Move function board_ddr_power_init() in a new file stpmic1 in
board/st/common to avoid duplicated code in each board using
stpmic1

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

diff --git a/board/dhelectronics/dh_stm32mp1/Makefile b/board/dhelectronics/dh_stm32mp1/Makefile
index e8f218da085ea62b394dded094974f044a1704d6..5758d9816bbde1acde10763c32929d027b0fe0e4 100644 (file)
--- a/board/dhelectronics/dh_stm32mp1/Makefile
+++ b/board/dhelectronics/dh_stm32mp1/Makefile
@@ -7,7 +7,7 @@ ifdef CONFIG_SPL_BUILD
 obj-y += ../../st/stm32mp1/spl.o
 endif
 
-obj-y += ../../st/stm32mp1/board.o board.o
+obj-y += ../../st/common/stpmic1.o board.o
 
 obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += ../../st/common/stm32mp_mtdparts.o
 obj-$(CONFIG_SET_DFU_ALT_INFO) += ../../st/common/stm32mp_dfu.o

diff --git a/board/st/common/Makefile b/board/st/common/Makefile
index aa030bacd81dbfdc1ec5a0bbc23218f1ca671e0b..012bfbbe8eea7ec90b11e5f3ac25b1dcdb8e3821 100644 (file)
--- a/board/st/common/Makefile
+++ b/board/st/common/Makefile
@@ -4,6 +4,7 @@
 #
 
 obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o
+obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
 
 ifeq ($(CONFIG_ARCH_STM32MP),y)
 obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += stm32mp_mtdparts.o

diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
new file mode 100644 (file)
index 0000000..41111c5
--- /dev/null
+++ b/board/st/common/stpmic1.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/ddr.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/stpmic1.h>
+
+int board_ddr_power_init(enum ddr_type ddr_type)
+{
+       struct udevice *dev;
+       bool buck3_at_1800000v = false;
+       int ret;
+       u32 buck2;
+
+       ret = uclass_get_device_by_driver(UCLASS_PMIC,
+                                         DM_GET_DRIVER(pmic_stpmic1), &dev);
+       if (ret)
+               /* No PMIC on board */
+               return 0;
+
+       switch (ddr_type) {
+       case STM32MP_DDR3:
+               /* VTT = Set LDO3 to sync mode */
+               ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+               if (ret < 0)
+                       return ret;
+
+               ret &= ~STPMIC1_LDO3_MODE;
+               ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+               ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
+
+               ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+                                    ret);
+               if (ret < 0)
+                       return ret;
+
+               /* VDD_DDR = Set BUCK2 to 1.35V */
+               ret = pmic_clrsetbits(dev,
+                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+                                     STPMIC1_BUCK_VOUT_MASK,
+                                     STPMIC1_BUCK2_1350000V);
+               if (ret < 0)
+                       return ret;
+
+               /* Enable VDD_DDR = BUCK2 */
+               ret = pmic_clrsetbits(dev,
+                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+                                     STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+               if (ret < 0)
+                       return ret;
+
+               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+               /* Enable VREF */
+               ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+                                     STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+               if (ret < 0)
+                       return ret;
+
+               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+               /* Enable VTT = LDO3 */
+               ret = pmic_clrsetbits(dev,
+                                     STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+                                     STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+               if (ret < 0)
+                       return ret;
+
+               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+               break;
+
+       case STM32MP_LPDDR2_16:
+       case STM32MP_LPDDR2_32:
+       case STM32MP_LPDDR3_16:
+       case STM32MP_LPDDR3_32:
+               /*
+                * configure VDD_DDR1 = LDO3
+                * Set LDO3 to 1.8V
+                * + bypass mode if BUCK3 = 1.8V
+                * + normal mode if BUCK3 != 1.8V
+                */
+               ret = pmic_reg_read(dev,
+                                   STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
+               if (ret < 0)
+                       return ret;
+
+               if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
+                       buck3_at_1800000v = true;
+
+               ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+               if (ret < 0)
+                       return ret;
+
+               ret &= ~STPMIC1_LDO3_MODE;
+               ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+               ret |= STPMIC1_LDO3_1800000;
+               if (buck3_at_1800000v)
+                       ret |= STPMIC1_LDO3_MODE;
+
+               ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+                                    ret);
+               if (ret < 0)
+                       return ret;
+
+               /* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
+               switch (ddr_type) {
+               case STM32MP_LPDDR2_32:
+               case STM32MP_LPDDR3_32:
+                       buck2 = STPMIC1_BUCK2_1250000V;
+                       break;
+               default:
+               case STM32MP_LPDDR2_16:
+               case STM32MP_LPDDR3_16:
+                       buck2 = STPMIC1_BUCK2_1200000V;
+                       break;
+               }
+
+               ret = pmic_clrsetbits(dev,
+                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+                                     STPMIC1_BUCK_VOUT_MASK,
+                                     buck2);
+               if (ret < 0)
+                       return ret;
+
+               /* Enable VDD_DDR1 = LDO3 */
+               ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+                                     STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+               if (ret < 0)
+                       return ret;
+
+               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+               /* Enable VDD_DDR2 =BUCK2 */
+               ret = pmic_clrsetbits(dev,
+                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+                                     STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+               if (ret < 0)
+                       return ret;
+
+               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+               /* Enable VREF */
+               ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+                                     STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+               if (ret < 0)
+                       return ret;
+
+               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+               break;
+
+       default:
+               break;
+       };
+
+       return 0;
+}

diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c
index c218d37ecce64ab7bb79de0992e071db7ad6004a..00c61c288640b231b7d4d8100793d2b5adac2a96 100644 (file)
--- a/board/st/stm32mp1/board.c
+++ b/board/st/stm32mp1/board.c
@@ -4,13 +4,9 @@
  */
 
 #include <common.h>
-#include <dm.h>
 #include <asm/io.h>
-#include <asm/arch/ddr.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
-#include <power/pmic.h>
-#include <power/stpmic1.h>
 
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 void board_debug_uart_init(void)
@@ -38,157 +34,3 @@ void board_debug_uart_init(void)
 #endif
 }
 #endif
-
-#ifdef CONFIG_PMIC_STPMIC1
-int board_ddr_power_init(enum ddr_type ddr_type)
-{
-       struct udevice *dev;
-       bool buck3_at_1800000v = false;
-       int ret;
-       u32 buck2;
-
-       ret = uclass_get_device_by_driver(UCLASS_PMIC,
-                                         DM_GET_DRIVER(pmic_stpmic1), &dev);
-       if (ret)
-               /* No PMIC on board */
-               return 0;
-
-       switch (ddr_type) {
-       case STM32MP_DDR3:
-               /* VTT = Set LDO3 to sync mode */
-               ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
-               if (ret < 0)
-                       return ret;
-
-               ret &= ~STPMIC1_LDO3_MODE;
-               ret &= ~STPMIC1_LDO12356_VOUT_MASK;
-               ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
-
-               ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-                                    ret);
-               if (ret < 0)
-                       return ret;
-
-               /* VDD_DDR = Set BUCK2 to 1.35V */
-               ret = pmic_clrsetbits(dev,
-                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-                                     STPMIC1_BUCK_VOUT_MASK,
-                                     STPMIC1_BUCK2_1350000V);
-               if (ret < 0)
-                       return ret;
-
-               /* Enable VDD_DDR = BUCK2 */
-               ret = pmic_clrsetbits(dev,
-                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-                                     STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
-               if (ret < 0)
-                       return ret;
-
-               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-               /* Enable VREF */
-               ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
-                                     STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
-               if (ret < 0)
-                       return ret;
-
-               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-               /* Enable VTT = LDO3 */
-               ret = pmic_clrsetbits(dev,
-                                     STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-                                     STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
-               if (ret < 0)
-                       return ret;
-
-               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-               break;
-
-       case STM32MP_LPDDR2_16:
-       case STM32MP_LPDDR2_32:
-       case STM32MP_LPDDR3_16:
-       case STM32MP_LPDDR3_32:
-               /*
-                * configure VDD_DDR1 = LDO3
-                * Set LDO3 to 1.8V
-                * + bypass mode if BUCK3 = 1.8V
-                * + normal mode if BUCK3 != 1.8V
-                */
-               ret = pmic_reg_read(dev,
-                                   STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
-               if (ret < 0)
-                       return ret;
-
-               if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
-                       buck3_at_1800000v = true;
-
-               ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
-               if (ret < 0)
-                       return ret;
-
-               ret &= ~STPMIC1_LDO3_MODE;
-               ret &= ~STPMIC1_LDO12356_VOUT_MASK;
-               ret |= STPMIC1_LDO3_1800000;
-               if (buck3_at_1800000v)
-                       ret |= STPMIC1_LDO3_MODE;
-
-               ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-                                    ret);
-               if (ret < 0)
-                       return ret;
-
-               /* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
-               switch (ddr_type) {
-               case STM32MP_LPDDR2_32:
-               case STM32MP_LPDDR3_32:
-                       buck2 = STPMIC1_BUCK2_1250000V;
-                       break;
-               default:
-               case STM32MP_LPDDR2_16:
-               case STM32MP_LPDDR3_16:
-                       buck2 = STPMIC1_BUCK2_1200000V;
-                       break;
-               }
-
-               ret = pmic_clrsetbits(dev,
-                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-                                     STPMIC1_BUCK_VOUT_MASK,
-                                     buck2);
-               if (ret < 0)
-                       return ret;
-
-               /* Enable VDD_DDR1 = LDO3 */
-               ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
-                                     STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
-               if (ret < 0)
-                       return ret;
-
-               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-               /* Enable VDD_DDR2 =BUCK2 */
-               ret = pmic_clrsetbits(dev,
-                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
-                                     STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
-               if (ret < 0)
-                       return ret;
-
-               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-               /* Enable VREF */
-               ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
-                                     STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
-               if (ret < 0)
-                       return ret;
-
-               mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
-               break;
-
-       default:
-               break;
-       };
-
-       return 0;
-}
-#endif