]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
Convert CONFIG_SPL_COMMON_INIT_DDR to Kconfig
authorTom Rini <trini@konsulko.com>
Sat, 21 May 2022 18:44:28 +0000 (14:44 -0400)
committerTom Rini <trini@konsulko.com>
Mon, 6 Jun 2022 16:09:12 +0000 (12:09 -0400)
This converts the following to Kconfig:
   CONFIG_SPL_COMMON_INIT_DDR

Signed-off-by: Tom Rini <trini@konsulko.com>
47 files changed:
README
board/freescale/p1010rdb/tlb.c
board/freescale/p1_p2_rdb_pc/tlb.c
configs/P1010RDB-PA_36BIT_NAND_defconfig
configs/P1010RDB-PA_36BIT_NOR_defconfig
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PA_NAND_defconfig
configs/P1010RDB-PA_NOR_defconfig
configs/P1010RDB-PA_SDCARD_defconfig
configs/P1010RDB-PA_SPIFLASH_defconfig
configs/P1010RDB-PB_36BIT_NAND_defconfig
configs/P1010RDB-PB_36BIT_NOR_defconfig
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PB_NAND_defconfig
configs/P1010RDB-PB_NOR_defconfig
configs/P1010RDB-PB_SDCARD_defconfig
configs/P1010RDB-PB_SPIFLASH_defconfig
configs/P1020RDB-PC_36BIT_NAND_defconfig
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
configs/P1020RDB-PC_36BIT_defconfig
configs/P1020RDB-PC_NAND_defconfig
configs/P1020RDB-PC_SDCARD_defconfig
configs/P1020RDB-PC_SPIFLASH_defconfig
configs/P1020RDB-PC_defconfig
configs/P1020RDB-PD_NAND_defconfig
configs/P1020RDB-PD_SDCARD_defconfig
configs/P1020RDB-PD_SPIFLASH_defconfig
configs/P1020RDB-PD_defconfig
configs/P2020RDB-PC_36BIT_NAND_defconfig
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
configs/P2020RDB-PC_36BIT_defconfig
configs/P2020RDB-PC_NAND_defconfig
configs/P2020RDB-PC_SDCARD_defconfig
configs/P2020RDB-PC_SPIFLASH_defconfig
configs/P2020RDB-PC_defconfig
drivers/ddr/fsl/Kconfig
include/configs/P1010RDB.h
include/configs/T102xRDB.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240RDB.h
include/configs/p1_p2_rdb_pc.h

diff --git a/README b/README
index 9f1561b92ca3c467a0028977e449f86826f12c0f..d6ff909e9a44d6ca8fe97244f197af17f719f4ed 100644 (file)
--- a/README
+++ b/README
@@ -1712,10 +1712,6 @@ The following options need to be configured:
                Support for a lightweight UBI (fastmap) scanner and
                loader
 
-               CONFIG_SPL_COMMON_INIT_DDR
-               Set for common ddr init with serial presence detect in
-               SPL binary.
-
                CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
                CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
                CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
index 04faefe994d0a205e655b7f3f775370345b85ee0..7992666e930785ddab4135f393c1f097a532370e 100644 (file)
@@ -72,8 +72,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 7, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT) || \
-       (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 8, BOOKE_PAGESZ_1G, 1),
index 5931ec650bd87270feb27d00877ebc5ff127bf92..6ded38ac683e543a60f3e343149bd1f290db6510 100644 (file)
@@ -77,8 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT) || \
-       (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
        /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
index 6b8c424c13b946887a91049750bfa5065620f9ae..f6426f0c171c8c378ddba459ecf011576f7462cd 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index 68cb2b14f1de1a12092d2aeebe980dc776c68052..7040c598a96c04681de9ac50a427c4a6f6cc954c 100644 (file)
@@ -49,6 +49,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -89,3 +90,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_FSL=y
 CONFIG_ADDR_MAP=y
+CONFIG_COMMON_INIT_DDR=y
index 235bb23593dfe15461045346ff1845ea70742cc2..57ad4b4485a39bc2bcb7418683c33b4802bd4616 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 933572f855b8937770dbafd49668dd549db2990d..ce5f1fd27628c9ab393ab8ced422fa94888558fc 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 6731429d53262f6ff8d973d43630728d830f1dcf..fca971bcf43f08a65c144f833474e804b48de25d 100644 (file)
@@ -67,6 +67,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index 95bd7861bdb548faff52ecdfae36dcfa78a698e6..d1046698d356ef3e6f3c673bbd93a038b5d031b8 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -87,3 +88,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_FSL=y
+CONFIG_COMMON_INIT_DDR=y
index 87116c11fc08867c78a57a5e35fc0c71f722b5f4..44d3512db221a3a7c1f970d0c5a41a6466d07400 100644 (file)
@@ -59,6 +59,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 4d0b405bb7d086616d3786aaa7da24e13f1570d3..5e6d0c234450642992ff1abe9bc5063e762b6600 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 2e9f9ee0c2240ef554e2d2ae47b93eee9c2b1654..39391699499b679b69d85e243ea4940503ff6fef 100644 (file)
@@ -69,6 +69,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index 26040927c89041cb0bb453ae9c53c1df9b0784bf..9692aaeaa70cb935430582e65d0b1d39ddfcb0e4 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -91,3 +92,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_FSL=y
 CONFIG_ADDR_MAP=y
+CONFIG_COMMON_INIT_DDR=y
index cf00a72f409c22ead1bf3355f10dbbb416e5f100..4e5e92d9670054f2a80248555705aeadb9a0b094 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 996b60d8b316eba99ac049172aee0dd909a4158a..f67961d83151951b7705eccce93db3e976d8afa8 100644 (file)
@@ -64,6 +64,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 42981c5a11d491c2b68e7af8940634fe1303eac8..da189ce8569f4c2e999db222ff3e26d82d9b5854 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index 3f9fa6b81815c38d07e9ba504f2ad2b79469e157..ca2ce61a1d46a6457502b881c66e93aa959b861c 100644 (file)
@@ -49,6 +49,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -89,3 +90,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_FSL=y
+CONFIG_COMMON_INIT_DDR=y
index 34f1a5f2b6ff23344cf986fc88c80d143440fdda..b5d097add8f9ae7c3df4e2f574d0a9be0e376f22 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index e48b0d1807f40a5395b7ba64850fc2798d5680cd..62d8e77745ce4805f5b15c0a1e82cb22549a7e3b 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 8ca01a0adc3d976214724bfbdfe2998a96fdd4cc..e9a7237a0805f9965655ea91f328d8f529f75bcb 100644 (file)
@@ -78,6 +78,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index 2dfb279d35b9ae505ca6fc0296a78d161f1a98de..6c47be30b7246d36b22312e0b8f462ce29135bd2 100644 (file)
@@ -69,6 +69,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 21aaa20461046e801a0293025e82d796e99ce907..3b2e7ce1118dffae105037a97278b22f060e08c8 100644 (file)
@@ -72,6 +72,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 0bf940b9c0425a8a504692474713e4bd57b5df92..f3bbb60485988804dec0a0eef0e4ab5c536cfbc0 100644 (file)
@@ -58,6 +58,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -101,3 +102,4 @@ CONFIG_USB=y
 CONFIG_USB_EHCI_FSL=y
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
+CONFIG_COMMON_INIT_DDR=y
index fe3ef2ea7502d2eda6f9fddf6267e66e4f37d857..cf211c7f5d556d3a1a12bb576cae79d5e7c9e441 100644 (file)
@@ -77,6 +77,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index 77e791f9e323484edd9f779ada67c4c2259cdaa9..55dc19d658aad92a90e498ec9a05059cfe0da3ba 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 47f42e847baaa6c8fd0ed854acbdd6349c014d47..c4391ed5424ccef1309f979c14393a28b3e1f63e 100644 (file)
@@ -71,6 +71,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 9ecae6c8b26e652b332ecbb2e5995596758292b8..7e20aa78875b255ef6edac4d046808caf2084e2e 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -99,3 +100,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_FSL=y
 CONFIG_USB_STORAGE=y
+CONFIG_COMMON_INIT_DDR=y
index f2608fc353edd7f1e83a96a7db10f816932b65c2..c85ec6d25201d8d77d1c0e9c81446d30900080f3 100644 (file)
@@ -80,6 +80,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index db9c782ffefacdd743d07fe6faa8af5c0bb8e110..a1bbb639257c72c1ed704384bcda6fca3ca677dc 100644 (file)
@@ -71,6 +71,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 236f07bd0e133bf733f5441cbf2744e419ad4990..e859587ccd3ca7ad33c349606dcc03b53a225a9e 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 1f40e8d2abfad8558028328e9723e6fc7560046b..966b9de5c7957f120dbb42b603533403a96df44e 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -103,3 +104,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_FSL=y
 CONFIG_USB_STORAGE=y
+CONFIG_COMMON_INIT_DDR=y
index 72b7f7b70460c22b94a1064648876050ab4f25ea..eefc72e49874874769c77c5ce79207feccd9e19b 100644 (file)
@@ -82,6 +82,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index b9604a7d5ab85e5c2705b336bd95e4c345bdf00a..5ac2f8c566d4d89584ce0de268a6b9bbcaeac1a3 100644 (file)
@@ -73,6 +73,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 4740e884e2e2db84b79c3dc43c3d8c1a4c585fe9..6150b84d11b7d1b8bf78f6e5cd3097e614094a55 100644 (file)
@@ -76,6 +76,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 945a031c07b3742b608dc9565cc1027ac1917984..fc22e6243194fc40e8915e2a534c9fb380ec9f07 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -106,3 +107,4 @@ CONFIG_USB=y
 CONFIG_USB_EHCI_FSL=y
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
+CONFIG_COMMON_INIT_DDR=y
index 03e0d74cb9d08e21f30c46782e9c2c69bbf0147c..dc94e25375cb6bf9033a86f0eb03bcd8fef7ffa8 100644 (file)
@@ -81,6 +81,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_TPL_SYS_I2C_LEGACY=y
index 80eb5f4bd9043de7f2d102145031dc5731b3d2ef..4f33a697cda053fccbc3298fa6096cbee1bb3070 100644 (file)
@@ -72,6 +72,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 85e5546e1ab5974f7ae06fc31b4009346b894d5e..e63cd161ddba81b6bd909d0c1525607b743e0b8e 100644 (file)
@@ -75,6 +75,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 8029c630c8652de18ec20ae180573979fcebe325..dd316f540fb14270410045ef0c8041565d872a8f 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
 CONFIG_SYS_BR3_PRELIM_BOOL=y
 CONFIG_SYS_BR3_PRELIM=0xFFA00801
 CONFIG_SYS_OR3_PRELIM=0xFFF009F7
+CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -104,3 +105,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_FSL=y
 CONFIG_USB_STORAGE=y
+CONFIG_COMMON_INIT_DDR=y
index 5925fe9e287c08138c740245a9de1a6eb3b1408c..fe69bef3d3aea0afe0922a7898914f2857be2bef 100644 (file)
@@ -263,6 +263,20 @@ config SYS_OR7_PRELIM
        depends on SYS_BR7_PRELIM_BOOL
 endmenu
 
+if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
+       TARGET_P1020RDB_PD || TARGET_P2020RDB
+
+config COMMON_INIT_DDR
+       bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
+
+config SPL_COMMON_INIT_DDR
+       bool "Do not have a TLB entry to cover common DDR init with SPD in SPL"
+
+config TPL_COMMON_INIT_DDR
+       bool "Do not have a TLB entry to cover common DDR init with SPD in TPL"
+
+endif
+
 config SYS_FSL_ERRATUM_A008378
        bool
 
index 734c33bd6a3be5b2f80179134452fa75f00113aa..ffd2cf943d279e3c2020b686daf18fb7697aac06 100644 (file)
@@ -22,9 +22,6 @@
 #define CONFIG_SYS_MMC_U_BOOT_START    (0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (96 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
 #endif
 
 #ifdef CONFIG_SPIFLASH
@@ -39,9 +36,6 @@
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (96 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
 #endif
 #endif
 
@@ -57,7 +51,6 @@
 #else
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (576 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x11000000)
index fcc31a0401bca590fbbb60d3a8f5397329e1f5a0..5de7b7c2dbf20b8e57c0a8ec3247178a87db234e 100644 (file)
@@ -23,7 +23,6 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define RESET_VECTOR_OFFSET            0x27FFC
 #define BOOT_PAGE_OFFSET               0x27000
-#define CONFIG_SPL_COMMON_INIT_DDR
 
 #ifdef CONFIG_MTD_RAW_NAND
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (768 << 10)
index 9f7ba9bd804946cf6f4c28b45278c9e514fbad8c..a7530693e7dc28b5a09f2251ff55df31b2105afd 100644 (file)
@@ -15,7 +15,6 @@
 #include <asm/config_mpc85xx.h>
 
 #ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SPL_COMMON_INIT_DDR
 #define RESET_VECTOR_OFFSET            0x27FFC
 #define BOOT_PAGE_OFFSET               0x27000
 
index 10bbf6e76f25d0d0d7a0c85b9d31193a3cc4af4e..d6bb8d18f904b8153a2ac745bd3d31869c7a0702 100644 (file)
@@ -31,7 +31,6 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define RESET_VECTOR_OFFSET            0x27FFC
 #define BOOT_PAGE_OFFSET               0x27000
-#define CONFIG_SPL_COMMON_INIT_DDR
 
 #ifdef CONFIG_MTD_RAW_NAND
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (768 << 10)
index a186ae3304853e4d3ae6a8098ebc502d46c1c7ce..350ecf1d2beb44938594c2f0ae5a2aadc4ec8a73 100644 (file)
@@ -26,7 +26,6 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define RESET_VECTOR_OFFSET            0x27FFC
 #define BOOT_PAGE_OFFSET               0x27000
-#define CONFIG_SPL_COMMON_INIT_DDR
 
 #ifdef CONFIG_MTD_RAW_NAND
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (768 << 10)
index c565e94023d83c1d2af5fcd5555485600d56b75c..9a3dd14abdb3aee7524cbe8348b370508b95f129 100644 (file)
@@ -36,8 +36,6 @@
 #endif
 #endif
 
-#define CONFIG_SPL_COMMON_INIT_DDR
-
 #endif
 #endif /* CONFIG_RAMBOOT_PBL */
 
index 2f65afe38bb6ee0ab5a8e8c8a565a61f468f47a9..bb44372d6defbf70c0e5ddd8a1ef90deb6fdea2e 100644 (file)
@@ -83,9 +83,6 @@
 #define CONFIG_SYS_MMC_U_BOOT_START    (0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (128 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
 #elif defined(CONFIG_SPIFLASH)
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (128 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
 #elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (832 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x11000000)