Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* Copyright 2004, 2011 Freescale Semiconductor.
*/
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#include <config.h>
#include <clock_legacy.h>
#include <linux/types.h>
u_char cm_reserved[248]; /* Total 256 bytes */
} cadmus_reg_t;
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unsigned int
get_board_version(void)
{
return cadmus->cm_ver;
}
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unsigned long
get_board_sys_clk(void)
{
}
}
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unsigned int
get_pci_slot(void)
{
return ((cadmus->cm_csr >> 6) & 0x3) + 1;
}
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unsigned int
get_pci_dual(void)
{
#ifndef __CADMUS_H_
#define __CADMUS_H_
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/*
* CADMUS Board System Register interface.
*/
*/
extern unsigned long get_board_sys_clk(void);
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/*
* Returns 1 - 4, as found in the USER CSR[6:7] bits.
*/
extern unsigned int get_pci_slot(void);
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/*
* Returns PCI DUAL as found in CM_PCI[3].
*/
extern unsigned int get_pci_dual(void);
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#endif /* __CADMUS_H_ */
#ifndef __EEPROM_H_
#define __EEPROM_H_
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/*
* EEPROM Board System Register interface.
*/
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/*
* CPU Board Revision
*/
*/
extern unsigned int get_cpu_board_revision(void);
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#endif /* __CADMUS_H_ */
}
#endif
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/* This function return length of public key.*/
static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
{
return 0;
}
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/* haddr - Address of the header of image to be validated.
* arg_hash_str - Option hash string. If provided, this
* overrides the key hash in the SFP fuses.
{ 0xd0000, 0x1 },
};
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/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
{ 0xd0000, 0x1 },
};
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/* P1 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x0 },
{ 0xd0000, 0x1 },
};
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/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
}
#endif
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int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
#define DDR_SIZE 0x40000000
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int checkboard(void)
{
puts("Board: LS1021AIOT\n");
return 0;
}
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#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
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/* Enable ZQ calibration */
popts->zq_en = 1;
else
pbsp = udimms[ctrl_num];
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/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
else
pbsp = udimms[ctrl_num];
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/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
udimm2, /* DP-DDR doesn't support RDIMM */
};
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#endif
return 0;
};
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int dram_init(void)
{
unsigned long junk = 0xa5a59696;
return 0;
};
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int testdram(void)
{
/* TODO: XXX XXX XXX */
}
#endif /* CONFIG_IDE */
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#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(struct bd_info *bis)
{
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
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out_be32(&sdp->sdmr, 0x018d0000);
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
* Copyright 2008 Freescale Semiconductor, Inc.
*/
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#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int cscmr1, ccgr6;
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/* Turn off EIM clock */
ccgr6 = readl(&imx_ccm->CCGR6);
ccgr6 &= ~(0x3 << 10);
}
#endif
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static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
if (ret != 0)
return ret;
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if (is_mx6dqp()) {
/* set SW2 staby volatage 0.975V*/
value = pmic_reg_read(dev, PFUZE100_SW2STBY);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
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/* Init mode to APS_PFM */
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
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/* Init mode to APS_PFM */
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
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static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
}
#endif
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int misc_init_r(void)
{
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u8 boot_config2; /* 0x1A - Boot config override register*/
};
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/* Pointer to the CPLD register set */
u8 cpld_read(unsigned int reg);
DEFAULT_FM_MDIO_NAME));
}
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cpu_eth_init(bis);
#endif
#define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e
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/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
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/* *I*G* - PCIe 4, 0xc0000000 */
SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
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/* *I*G* - PCIe 4, 0xc0000000 */
SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
else
pbsp = udimms[0];
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
}
#endif
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static void setup_iomux_qspi(void)
{
static const iomux_v3_cfg_t qspi0_pads[] = {
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