x86: chromebook_link: dts: Add PCH and LPC devices

The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.

Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 2639ec24139973cc9f637eecc134346f34855ca3..37f373148cf08319ecab034aa3af87a39f13796e 100644 (file)
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -142,7 +142,7 @@ int arch_cpu_init_dm(void)
        /* TODO(sjg@chromium.org): Get rid of gd->hose */
        gd->hose = hose;
 
-       node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+       node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
        if (node < 0)
                return -ENOENT;
        ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index c20e180329122abb348d999171fdb6bdfecf3c60..bc1a0f06fbe31d6829a7a1c75c38c50c0c768a11 100644 (file)
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -510,7 +510,7 @@ int lpc_init(struct pci_controller *hose, pci_dev_t dev)
        pci_write_bar32(hose, dev, 3, 0x800);
        pci_write_bar32(hose, dev, 4, 0x900);
 
-       node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+       node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
        if (node < 0)
                return -ENOENT;
 
@@ -568,3 +568,14 @@ void lpc_enable(pci_dev_t dev)
        writew(0x0010, RCB_REG(DISPBDF));
        setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
 }
+
+static const struct udevice_id bd82x6x_lpc_ids[] = {
+       { .compatible = "intel,bd82x6x-lpc" },
+       { }
+};
+
+U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
+       .name           = "lpc",
+       .id             = UCLASS_LPC,
+       .of_match       = bd82x6x_lpc_ids,
+};

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 0a845f29718d1a76587a555d1e57d24ef1cbb466..b450c3c55f5664de00fb1fcb0a4396f02b6783cc 100644 (file)
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -8,7 +8,7 @@
        compatible = "google,link", "intel,celeron-ivybridge";
 
        aliases {
-               spi0 = "/spi";
+               spi0 = "/pci/pch/spi";
        };
 
        config {
@@ -151,26 +151,6 @@
                };
        };
 
-       spi {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               compatible = "intel,ich-spi";
-               spi-flash@0 {
-                       #size-cells = <1>;
-                       #address-cells = <1>;
-                       reg = <0>;
-                       compatible = "winbond,w25q64", "spi-flash";
-                       memory-map = <0xff800000 0x00800000>;
-                       rw-mrc-cache {
-                               label = "rw-mrc-cache";
-                               /* Alignment: 4k (for updating) */
-                               reg = <0x003e0000 0x00010000>;
-                               type = "wiped";
-                               wipe-value = [ff];
-                       };
-               };
-       };
-
        pci {
                compatible = "intel,pci-ivybridge", "pci-x86";
                #address-cells = <3>;
@@ -199,9 +179,10 @@
                        intel,pch-backlight = <0x04000000>;
                };
 
-               lpc {
+               pch {
                        reg = <0x0000f800 0 0 0 0>;
                        compatible = "intel,bd82x6x";
+                       u-boot,dm-pre-reloc;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        gen-dec = <0x800 0xfc 0x900 0xfc>;
@@ -212,17 +193,44 @@
                                                1 0 0 0 0 0 0 0>;
                        /* Enable EC SMI source */
                        intel,alt-gp-smi-enable = <0x0100>;
+                       spi {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "intel,ich-spi";
+                               spi-flash@0 {
+                                       #size-cells = <1>;
+                                       #address-cells = <1>;
+                                       reg = <0>;
+                                       compatible = "winbond,w25q64",
+                                                       "spi-flash";
+                                       memory-map = <0xff800000 0x00800000>;
+                                       rw-mrc-cache {
+                                               label = "rw-mrc-cache";
+                                               reg = <0x003e0000 0x00010000>;
+                                               type = "wiped";
+                                               wipe-value = [ff];
+                                       };
+                               };
+                       };
 
-                       cros-ec@200 {
-                               compatible = "google,cros-ec";
-                               reg = <0x204 1 0x200 1 0x880 0x80>;
-
-                               /* Describes the flash memory within the EC */
+                       lpc {
+                               compatible = "intel,bd82x6x-lpc";
                                #address-cells = <1>;
-                               #size-cells = <1>;
-                               flash@8000000 {
-                                       reg = <0x08000000 0x20000>;
-                                       erase-value = <0xff>;
+                               #size-cells = <0>;
+                               cros-ec@200 {
+                                       compatible = "google,cros-ec";
+                                       reg = <0x204 1 0x200 1 0x880 0x80>;
+
+                                       /*
+                                        * Describes the flash memory within
+                                        * the EC
+                                        */
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+                                       flash@8000000 {
+                                               reg = <0x08000000 0x20000>;
+                                               erase-value = <0xff>;
+                                       };
                                };
                        };
                };

diff --git a/include/fdtdec.h b/include/fdtdec.h
index c39ad90f02097063e2297c1909d45a207b6d2cbb..e45e2ab98082c091ab1f56ff1582c8127778d5b5 100644 (file)
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -169,6 +169,7 @@ enum fdt_compat_id {
        COMPAT_INTEL_ICH_SPI,           /* Intel ICH7/9 SPI controller */
        COMPAT_INTEL_QRK_MRC,           /* Intel Quark MRC */
        COMPAT_SOCIONEXT_XHCI,          /* Socionext UniPhier xHCI */
+       COMPAT_INTEL_PCH,               /* Intel PCH */
 
        COMPAT_COUNT,
 };

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 9fcc1bbea58bbf9d5a14dcda02496065a02ee762..6d7a251bc2c262ae06ff39599cadd7eee3318288 100644 (file)
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -67,7 +67,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
        COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
        COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
        COMPAT(PARADE_PS8625, "parade,ps8625"),
-       COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x"),
+       COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x-lpc"),
        COMPAT(INTEL_MICROCODE, "intel,microcode"),
        COMPAT(MEMORY_SPD, "memory-spd"),
        COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
@@ -77,6 +77,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
        COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
        COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
        COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
+       COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)