clk_free(&clk);
- if (ret == -ENOTSUPP) {
+ if (ret == -EINVAL) {
printf("clk ID %lu not supported yet\n",
aspeed_clk_names[i].id);
continue;
if (clk->map[sclk->id].set_rate)
return clk->map[sclk->id].set_rate(sclk, rate);
- return -ENOTSUPP;
+ return -EINVAL;
}
static int hsdk_cgu_disable(struct clk *sclk)
if (clk->map[sclk->id].disable)
return clk->map[sclk->id].disable(sclk);
- return -ENOTSUPP;
+ return -EINVAL;
}
static const struct clk_ops hsdk_cgu_ops = {
__weak int __imx8_clk_enable(struct clk *clk, bool enable)
{
- return -ENOTSUPP;
+ return -EINVAL;
}
static int imx8_clk_disable(struct clk *clk)
clk_free(&clk);
- if (ret == -ENOTSUPP) {
+ if (ret == -EINVAL) {
printf("clk ID %lu not supported yet\n",
imx8_clk_names[i].id);
continue;
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
};
ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
};
ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
}
ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
};
ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
};
ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
__func__, clk->id);
return -EINVAL;
}
- return -ENOTSUPP;
+ return -EINVAL;
}
ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
break;
default:
kfree(pll);
- return ERR_PTR(-ENOTSUPP);
+ return ERR_PTR(-EINVAL);
}
pll->base = base;
if (ops->set_parent)
return ops->set_parent(bypass->bypassee, parent);
else
- return -ENOTSUPP;
+ return -EINVAL;
}
/*
* could fix this, but it's Probably Not Worth It (TM).
*/
if (probed)
- return -ENOTSUPP;
+ return -EINVAL;
base = dev_read_addr_ptr(dev_get_parent(dev));
if (!base)
return -EINVAL;
if (!periph_clk->can_gate)
- return -ENOTSUPP;
+ return -EINVAL;
if (enable)
clrbits_le32(priv->reg + CLK_DIS, periph_clk->disable_bit);
return old_rate;
if (!periph_clk->can_gate || !periph_clk->dividers)
- return -ENOTSUPP;
+ return -EINVAL;
parent_rate = get_parent_rate(priv, clk->id);
if (parent_rate == -EINVAL)
return -EINVAL;
if (!periph_clk->can_mux || !periph_clk->can_gate)
- return -ENOTSUPP;
+ return -EINVAL;
ret = clk_get_by_index(clk->dev, 0, &check_parent);
if (ret < 0)