]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx8m: ddr: Disable CA VREF Training for LPDDR4
authorYe Li <ye.li@nxp.com>
Fri, 19 Mar 2021 07:57:14 +0000 (15:57 +0800)
committerStefano Babic <sbabic@denx.de>
Thu, 8 Apr 2021 07:18:29 +0000 (09:18 +0200)
Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
but not set in 1D.  According to PHY training application node,
to enable the feature both 1D and 2D need set this field to 1,
otherwise the training result will be incorrect.
The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
MR12 value from message block (FSP structure). So update the LPDDR4
scripts of all mscale to clear CATrainOpt[0].

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
board/freescale/imx8mn_evk/lpddr4_timing_ld.c
board/freescale/imx8mp_evk/lpddr4_timing.c

index 5faa0021a73d7b1f90b8a92d7320bc887274415b..aa23c350945a2e060b109af396394ce5f3c3a354 100644 (file)
@@ -799,7 +799,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54008, 0x61 },
        { 0x54009, 0xc8 },
        { 0x5400b, 0x2 },
-       { 0x5400d, 0x100 },
        { 0x5400f, 0x100 },
        { 0x54010, 0x1f7f },
        { 0x54012, 0x310 },
index 9d069fc27a812f063bdc5eea607249661401e6cd..8c5306d5d206af7b9441b319e8ee589de5c90264 100755 (executable)
@@ -1298,7 +1298,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54008, 0x61 },
        { 0x54009, 0xc8 },
        { 0x5400b, 0x2 },
-       { 0x5400d, 0x100 },
        { 0x5400f, 0x100 },
        { 0x54010, 0x1f7f },
        { 0x54012, 0x310 },
@@ -1330,7 +1329,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54008, 0x61 },
        { 0x54009, 0xc8 },
        { 0x5400b, 0x2 },
-       { 0x5400d, 0x100 },
        { 0x5400f, 0x100 },
        { 0x54010, 0x1f7f },
        { 0x54012, 0x310 },