CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_AM57XX_EVM=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=600
CONFIG_TARGET_BRSMARC1=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBIT_MICKEY=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_X86=y
CONFIG_SYS_TEXT_BASE=0x1110000
CONFIG_SYS_MALLOC_F_LEN=0x3d00
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000
CONFIG_NR_DRAM_BANKS=8
CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_MINNIE=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_AM43XX=y
CONFIG_TARGET_CM_T43=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3368=y
CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_TARGET_K2G_EVM=y
CONFIG_ENV_SIZE=0x40000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3368=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_PINEBOOK_PRO_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
CONFIG_TARGET_PUMA_RK3399=y
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_ENV_SIZE=0x40000
CONFIG_MAX_CPUS=2
+CONFIG_SPL_DM_SPI=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_ENV_SIZE=0x6000
CONFIG_ENV_OFFSET=0x460000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROC_PC_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x6000
CONFIG_ENV_OFFSET=0x460000
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROC_PC_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROCKPRO64_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SIZE=0x20000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_ENV_OFFSET=0x200
CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_arria10"
CONFIG_ENV_OFFSET=0x4400
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_OFFSET=0x4400
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_OFFSET=0x4400
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_FIT=y
CONFIG_ENV_OFFSET=0x4400
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_OFFSET=0x4400
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_TARGET_SOCFPGA_IS1=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ENV_OFFSET=0x4400
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_OFFSET=0x4400
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_OFFSET=0x4400
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_TARGET_SOCFPGA_SR1500=y
CONFIG_ENV_OFFSET_REDUND=0xF0000
CONFIG_ENV_OFFSET=0x200
CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y
CONFIG_ENV_OFFSET_REDUND=0x110000
CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_ENV_OFFSET=0x280000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SIZE=0x4000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TARGET_DH_STM32MP1_PDK2=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SIZE=0x4000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TARGET_DH_STM32MP1_PDK2=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x100000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_ENV_SIZE=0x8000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_ENV_SIZE=0x8000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_ENV_SIZE=0x8000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0000000
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_SIZE=0x190
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_MALLOC_LEN=0x1000
+CONFIG_SPL_DM_SPI=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x0