powerpc/fsl_pci: Fix device tree fixups for newer platforms

We assumed that only a small set of compatiable strings would be needed
to find the PCIe device tree nodes to be fixed up.  However on newer
platforms the simple rules no longer work.  We need to allow specifying
the PCIe compatiable string for each individual SoC.

We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if
the default isn't sufficient.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/README b/README
index ed73981b94817bfb434d1de245a8b014823ab223..8bb9c8d6be2a1b4bc50ea6882dcb1e1f12956b0f 100644 (file)
--- a/README
+++ b/README
@@ -363,6 +363,11 @@ The following options need to be configured:
                system clock.  On most PQ3 devices this is 8, on newer QorIQ
                devices it can be 16 or 32.  The ratio varies from SoC to Soc.
 
+               CONFIG_SYS_FSL_PCIE_COMPAT
+
+               Defines the string to utilize when trying to match PCIe device
+               tree nodes for the given platform.
+
 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 41c2d20df5deab4fbfa3d56185fef760bbb69b09..d5c0aee52cdd7766b0df780d9d1a139e35691ea6 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -96,6 +96,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -175,6 +176,7 @@
 #define CONFIG_SYS_QMAN_NUM_PORTALS    3
 #define CONFIG_SYS_BMAN_NUM_PORTALS    3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x10000
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 
 #elif defined(CONFIG_P1020)
 #define CONFIG_MAX_CPUS                        2
@@ -216,6 +218,7 @@
 #define CONFIG_SYS_QMAN_NUM_PORTALS    3
 #define CONFIG_SYS_BMAN_NUM_PORTALS    3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x10000
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 
 /* P1024 is lower end variant of P1020 */
 #elif defined(CONFIG_P1024)
@@ -265,6 +268,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       32
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -280,6 +284,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       32
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -291,6 +296,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,p4080-pcie"
 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS                        8
@@ -305,6 +311,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS     2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,p4080-pcie"
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@@ -330,6 +337,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       32
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -345,6 +353,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS     2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       32
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111

diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index fc47a9f7ec8d2ed8d4d0a93a9357a96bd23629d7..49bd2bfa39d313770b0ac7483ab4cab634eeff85 100644 (file)
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -233,7 +233,7 @@ int fsl_pcie_init_board(int busno);
 #if !defined(CONFIG_PCI)
 #define FT_FSL_PCI_SETUP
 #elif defined(CONFIG_FSL_CORENET)
-#define FSL_PCIE_COMPAT        "fsl,p4080-pcie"
+#define FSL_PCIE_COMPAT        CONFIG_SYS_FSL_PCIE_COMPAT
 #define FT_FSL_PCI_SETUP \
        FT_FSL_PCIE1_SETUP; \
        FT_FSL_PCIE2_SETUP; \
@@ -242,7 +242,11 @@ int fsl_pcie_init_board(int busno);
 #define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
 #elif defined(CONFIG_MPC85xx)
 #define FSL_PCI_COMPAT "fsl,mpc8540-pci"
+#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
+#define FSL_PCIE_COMPAT        CONFIG_SYS_FSL_PCIE_COMPAT
+#else
 #define FSL_PCIE_COMPAT        "fsl,mpc8548-pcie"
+#endif
 #define FT_FSL_PCI_SETUP \
        FT_FSL_PCI1_SETUP; \
        FT_FSL_PCI2_SETUP; \